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/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
H A Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
H A Dhantro_g1_mpeg2_dec.c25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
[all …]
/linux/lib/crypto/arm64/
H A Dsha512-ce-core.S76 ld1 {v\rc1\().2d}, [x4], #16
78 add v5.2d, v\rc0\().2d, v\in0\().2d
79 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
81 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
82 add v\i3\().2d, v\i3\().2d, v5.2d
84 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
85 sha512su0 v\in0\().2d, v\in1\().2d
89 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
91 add v\i4\().2d, v\i1\().2d, v\i3\().2d
92 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/linux/arch/alpha/kernel/
H A Dentry.S75 stq $25, 120($sp)
92 .cfi_rel_offset $25, 120
121 ldq $25, 120($sp)
141 .cfi_restore $25
279 stq $25, 200($sp)
306 .cfi_rel_offset $25, 25*8
338 ldq $25, 200($sp)
365 .cfi_restore $25
687 #define V(n) stt $f##n, FR(n) macro
688 V( 0); V( 1); V( 2); V( 3)
[all …]
/linux/Documentation/fb/
H A Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
87 # 13 chars 25 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
[all …]
/linux/drivers/ata/
H A Dlibata-pata-timings.c31 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 },
32 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 },
41 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 },
42 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 },
43 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 },
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1) argument
58 #define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0) argument
/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek,mt7621-pcie.yaml26 v
31 v v v On Bus0
39 On Bus1 v On Bus2 v On Bus3 v
129 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
155 resets = <&rstctrl 25>;
156 clocks = <&clkctrl 25>;
169 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
/linux/include/linux/spi/
H A Dmxs-spi.h24 #define BM_SSP_CTRL0_READ (1 << 25)
36 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
71 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Diters.c34 int *v, i = zero; /* obscure initial value of i */ in iter_err_unsafe_c_loop() local
39 while ((v = bpf_iter_num_next(&it))) { in iter_err_unsafe_c_loop()
96 int *v; in iter_while_loop() local
101 while ((v = bpf_iter_num_next(&it))) { in iter_while_loop()
102 bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v); in iter_while_loop()
114 int *v; in iter_while_loop_auto_cleanup() local
119 while ((v = bpf_iter_num_next(&it))) { in iter_while_loop_auto_cleanup()
120 bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v); in iter_while_loop_auto_cleanup()
132 int *v; in iter_for_loop() local
137 for (v = bpf_iter_num_next(&it); v; v = bpf_iter_num_next(&it)) { in iter_for_loop()
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_tablet.py629 for v in self.parsed_rdesc.feature_reports.values():
630 if v.report_ID == rnum:
631 rdesc = v
643 for v in self.parsed_rdesc.feature_reports.values():
644 if v.report_ID == rnum:
645 rdesc = v
731 [pytest.param(v, id=k) for k, v in PenState.legal_transitions().items()],
744 pytest.param(v, id=k)
745 for k, v i
[all...]
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/linux/lib/crypto/
H A Dcurve25519-fiat32.c20 * fe limbs are bounded by 1.125*2^26,1.125*2^25,1.125*2^26,1.125*2^25,etc.
23 typedef struct fe { u32 v[10]; } fe; member
25 /* fe_loose limbs are bounded by 3.375*2^26,3.375*2^25,3.375*2^26,3.375*2^25,etc
28 typedef struct fe_loose { u32 v[10]; } fe_loose; member
42 h[1] = (a0>>26) | ((a1&((1<<19)-1))<< 6); /* (32-26) + 19 = 6+19 = 25 */ in fe_frombytes_impl()
44 h[3] = (a2>>13) | ((a3&((1<< 6)-1))<<19); /* (32-13) + 6 = 19+ 6 = 25 */ in fe_frombytes_impl()
46 h[5] = a4&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
47 h[6] = (a4>>25) | ((a5&((1<<19)-1))<< 7); /* (32-25) + 19 = 7+19 = 26 */ in fe_frombytes_impl()
48 h[7] = (a5>>19) | ((a6&((1<<12)-1))<<13); /* (32-19) + 12 = 13+12 = 25 */ in fe_frombytes_impl()
50 h[9] = (a7>> 6)&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
[all …]
/linux/drivers/net/hamradio/
H A Dbpqether.c3 * G8BPQ compatible "AX.25 via ethernet" driver release 004
7 * This is a "pseudo" network driver to allow AX.25 over Ethernet
15 * - user-level programs like the AX.25 utilities shouldn't
17 * - IP over ethernet encapsulated AX.25 was impossible
38 * BPQ 001 Joerg(DL1BKE) Extracted BPQ code from AX.25
86 "AX.25: bpqether driver version 004\n";
148 * Receive an AX.25 frame via an ethernet interface.
216 * Send an AX.25 frame via an ethernet interface
279 * Set AX.25 callsign
374 static void *bpq_seq_next(struct seq_file *seq, void *v, loff_t *pos) in bpq_seq_next() argument
[all …]
/linux/drivers/media/platform/sunxi/sun6i-mipi-csi2/
H A Dsun6i_mipi_csi2_reg.h17 #define SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(v) ((((v) - 1) << 8) & \ argument
19 #define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v) (((v) - 1) & GENMASK(1, 0)) argument
36 #define SUN6I_MIPI_CSI2_CH_INT_EN_LINE_SYNC_ERR BIT(25)
53 #define SUN6I_MIPI_CSI2_CH_INT_PD_LINE_SYNC_ERR BIT(25)
/linux/sound/soc/rockchip/
H A Drockchip_sai.h20 #define SAI_XCR_CSR_V(v) ((((v) & SAI_XCR_CSR_MASK) >> 20) + 1) argument
34 #define SAI_XCR_SBW_V(v) ((((v) & SAI_XCR_SBW_MASK) >> 5) + 1) argument
46 #define SAI_FSCR_FW_V(v) ((((v) & SAI_FSCR_FW_MASK) >> 0) + 1) argument
113 #define SAI_DMACR_RDL_V(v) ((((v) & SAI_DMACR_RDL_MASK) >> 16) + 1) argument
118 #define SAI_DMACR_TDL_V(v) (((v) & SAI_DMACR_TDL_MASK) >> 0) argument
125 #define SAI_INTCR_FSERR_MASK BIT(25)
126 #define SAI_INTCR_FSERR(x) ((x) << 25)
147 #define SAI_RX_PATH(x, v) ((v) << SAI_RX_PATH_SHIFT(x)) argument
150 #define SAI_TX_PATH(x, v) ((v) << SAI_TX_PATH_SHIFT(x)) argument
160 #define SAI_XSHIFT_LEFT_MASK GENMASK(25, 24)
/linux/drivers/net/wan/
H A DKconfig9 Wide Area Networks (WANs), such as X.25, Frame Relay and leased
37 Relay, synchronous Point-to-Point Protocol (PPP) and X.25.
88 tristate "X.25 protocol support"
91 Generic HDLC driver supporting X.25 over WAN connections.
95 comment "X.25/LAPB support is disabled"
185 Support for the FarSync T-Series X.21 (and V.35/V.24) cards by
189 8Mb/s (128K on V.24) using synchronous PPP, Cisco HDLC, raw HDLC,
190 Frame Relay or X.25/LAPB.
244 # X.25 network drivers
/linux/drivers/clk/versatile/
H A Dclk-icst.c74 * bits of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
81 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
89 * access the low eight bits of the v PLL divider. Bit 8 is tied low in vco_get()
96 vco->v = val & INTEGRATOR_AP_SYS_BITS; in vco_get()
106 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the in vco_get()
107 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies in vco_get()
108 * 33 or 25 MHz respectively. in vco_get()
113 vco->v = divxy ? 17 : 14; in vco_get()
121 * of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
128 vco->v = val & 0xFF; in vco_get()
[all …]
/linux/drivers/net/ethernet/altera/
H A Daltera_tse.h53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
73 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) argument
80 #define MAC_CMDCFG_ENA_10 BIT(25)
85 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) argument
86 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) argument
87 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALU argument
88 MAC_CMDCFG_ETH_SPEED_GET(v) global() argument
89 MAC_CMDCFG_PROMIS_EN_GET(v) global() argument
90 MAC_CMDCFG_PAD_EN_GET(v) global() argument
91 MAC_CMDCFG_CRC_FWD_GET(v) global() argument
92 MAC_CMDCFG_PAUSE_FWD_GET(v) global() argument
93 MAC_CMDCFG_PAUSE_IGNORE_GET(v) global() argument
94 MAC_CMDCFG_TX_ADDR_INS_GET(v) global() argument
95 MAC_CMDCFG_HD_ENA_GET(v) global() argument
96 MAC_CMDCFG_EXCESS_COL_GET(v) global() argument
97 MAC_CMDCFG_LATE_COL_GET(v) global() argument
98 MAC_CMDCFG_SW_RESET_GET(v) global() argument
99 MAC_CMDCFG_MHASH_SEL_GET(v) global() argument
100 MAC_CMDCFG_LOOP_ENA_GET(v) global() argument
101 MAC_CMDCFG_TX_ADDR_SEL_GET(v) global() argument
102 MAC_CMDCFG_MAGIC_ENA_GET(v) global() argument
103 MAC_CMDCFG_SLEEP_GET(v) global() argument
104 MAC_CMDCFG_WAKEUP_GET(v) global() argument
105 MAC_CMDCFG_XOFF_GEN_GET(v) global() argument
106 MAC_CMDCFG_CNTL_FRM_ENA_GET(v) global() argument
107 MAC_CMDCFG_NO_LGTH_CHECK_GET(v) global() argument
108 MAC_CMDCFG_ENA_10_GET(v) global() argument
109 MAC_CMDCFG_RX_ERR_DISC_GET(v) global() argument
110 MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) global() argument
111 MAC_CMDCFG_CNT_RESET_GET(v) global() argument
[all...]
/linux/drivers/iio/adc/
H A Dstm32-adc-core.h65 #define STM32F4_RES_MASK GENMASK(25, 24)
145 #define STM32H7_LINCALRDYW4 BIT(25)
168 #define STM32H7_OVSR_MASK GENMASK(25, 16) /* Correspond to OSVR field in datasheet */
169 #define STM32H7_OVSR(v) FIELD_PREP(STM32H7_OVSR_MASK, v) argument
171 #define STM32H7_OVSS(v) FIELD_PREP(STM32H7_OVSS_MASK, v) argument
242 #define STM32MP13_OVSR(v) FIELD_PREP(STM32MP13_OVSR_MASK, v) argument
244 #define STM32MP13_OVSS(v) FIELD_PREP(STM32MP13_OVSS_MASK, v) argument
/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_mipi_csi2_reg.h27 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LINE_CKSM_ERR_VC1 BIT(25)
82 #define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CKSM_ERR_VC1 BIT(25)
134 #define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_DLY_CYCLE(v) (((v) << 18) & \ argument
136 #define SUN8I_A83T_MIPI_CSI2_CFG_N_CHANNEL(v) ((((v) - 1) << 16) & \ argument
138 #define SUN8I_A83T_MIPI_CSI2_CFG_N_LANE(v) ((((v) - 1) << 4) & \ argument
/linux/drivers/watchdog/
H A Drealtek_otto_wdt.c10 * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
77 u32 v; in otto_wdt_start() local
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
80 v |= OTTO_WDT_CTRL_ENABLE; in otto_wdt_start()
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
89 u32 v; in otto_wdt_stop() local
91 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
92 v &= ~OTTO_WDT_CTRL_ENABLE; in otto_wdt_stop()
93 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
109 return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz); in otto_wdt_tick_ms()
[all …]
/linux/Documentation/userspace-api/media/dvb/
H A Dca_high_level.rst106 (25) ES type=[4] ES pid=[301] ES length =[0 (0x0)]
107 ca_message length is 25 (0x19) bytes
136 v
141 | v |
145 | v |
149 | v |
154 v
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ argument
32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-helios4.dts33 reg_12v: regulator-12v {
50 reg_5p0v_hdd: regulator-5v-hdd {
59 reg_5p0v_usb: regulator-5v-usb {
85 gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
129 pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */
136 pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */
254 no-1-8-v;

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