Lines Matching +full:25 +full:v

74 	 * bits of the v PLL divider. Bit 8 is tied low and always zero,
81 		vco->v = val & INTEGRATOR_AP_CM_BITS;
89 	 * access the low eight bits of the v PLL divider. Bit 8 is tied low
96 		vco->v = val & INTEGRATOR_AP_SYS_BITS;
106 	 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
107 	 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
108 	 * 33 or 25 MHz respectively.
113 		vco->v = divxy ? 17 : 14;
121 	 * of the v PLL divider. Bit 8 is tied low and always zero,
128 		vco->v = val & 0xFF;
135 		vco->v = (val >> 12) & 0xFF;
141 	vco->v = val & 0x1ff;
162 		val = vco.v & 0xFF;
163 		if (vco.v & 0x100)
172 		val = vco.v & 0xFF;
173 		if (vco.v & 0x100)
182 		val = (vco.v & 0xFF) | vco.s << 8;
183 		if (vco.v & 0x100)
190 		val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
191 		if (vco.v & 0x100)
199 		val = vco.v | (vco.r << 9) | (vco.s << 16);
274 		 * If we're below or less than halfway from 25 to 33 MHz
275 		 * select 25 MHz
471 	/* Minimum 25 MHz */
472 	.vd_min		= 25,