Searched +full:25 +full:gbase +full:- +full:sr (Results 1 – 2 of 2) sorted by relevance
1 /* SPDX-License-Identifier: GPL-2.0-only */4 * Copyright 2009-2018 Solarflare Communications Inc.5 * Copyright 2019-2020 Xilinx Inc.13 /* Power-on reset state */35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */38 /* The rest of these are firmware-defined */46 /* Values to be written to the per-port status dword in shared71 * | | \--- Response72 * | \------- Error73 * \------------------------------ Resync (always set)[all …]
3 * Copyright (c) 2007-2013 Broadcom Corporation13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be20 * WR - Write Clear (write 1 to clear the bit)32 /* [RW 1] Initiate the ATC array - reset all the valid bits */56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -[all …]