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/linux/lib/crypto/x86/
H A Dsha256-avx-asm.S110 g = %r10d define
143 h = g
144 g = f define
158 MY_ROR (25-11), y0 # y0 = e >> (25-11)
162 xor e, y0 # y0 = e ^ (e >> (25-11))
164 MY_ROR (11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
166 xor g, y2 # y2 = f^g
168 xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
169 and e, y2 # y2 = (f^g)&e
174 MY_ROR 6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
[all …]
H A Dsha256-ssse3-asm.S103 g = %r10d define
137 h = g
138 g = f define
152 ror $(25-11), y0 # y0 = e >> (25-11)
156 xor e, y0 # y0 = e ^ (e >> (25-11))
158 ror $(11-6), y0 # y0 = (e >> (11-6)) ^ (e >> (25-6))
161 xor g, y2 # y2 = f^g
163 xor e, y0 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
164 and e, y2 # y2 = (f^g)&e
169 ror $6, y0 # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
[all …]
H A Dsha256-avx2-asm.S105 g = %r10d define
143 h = g
144 g = f define
157 rorx $25, e, y0 # y0 = e >> 25 # S1A
166 xor y1, y0 # y0 = (e>>25) ^ (e>>11) # S1
167 xor g, y2 # y2 = f^g # CH
171 and e, y2 # y2 = (f^g)&e # CH
172 xor y1, y0 # y0 = (e>>25) ^ (e>>11) ^ (e>>6) # S1
181 xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
205 rorx $25, e, y0 # y0 = e >> 25 # S1A
[all …]
/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
21 * disp 0 ~ 4G larb0/1/2/3
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
261 #define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25)
290 #define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25)
336 #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0)
[all …]
H A Dmediatek,mt8188-memory-port.h42 #define SMI_L28_ID 25
46 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
49 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
54 * disp 0 ~ 4G larb0/1/2/3
55 * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23
56 * cam/mdp 8G ~ 12G the other larbs.
57 * N/A 12G ~ 16G
208 #define M4U_PORT_L11A_YUVO_T5_C MTK_M4U_ID(SMI_L11A_ID, 25)
240 #define M4U_PORT_L11B_YUVO_T5_C MTK_M4U_ID(SMI_L11B_ID, 25)
272 #define M4U_PORT_L11C_YUVO_T5_C MTK_M4U_ID(SMI_L11C_ID, 25)
[all …]
H A Dmt8186-memory-port.h15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
114 #define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25)
145 #define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25)
H A Dmediatek,mt8189-memory-port.h27 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
30 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
35 * disp/mdp 0 ~ 4G larb0/1/2
36 * vcodec 4G ~ 8G larb4/7
37 * imgsys/cam/ipesys 8G ~ 12G the other larbs.
38 * N/A 12G ~ 16G
142 #define M4U_L9_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L9_ID, 25)
175 #define M4U_L11_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L11_ID, 25)
H A Dmediatek,mt6893-memory-port.h18 * disp 0 ~ 4G larb0/2
19 * vcodec 4G ~ 8G larb4/5/7
20 * cam/mdp 8G ~ 12G larb9/11/13/14/16/17/18/19/20
122 #define M4U_PORT_L7_JPGENC_HUFF_OFFSET1_DISP MTK_M4U_DOM_ID(7, 25)
153 #define M4U_PORT_L9_IMG_MFB_WDMA1_MDP MTK_M4U_DOM_ID(9, 25)
186 #define M4U_PORT_L11_IMG_MFB_WDMA1_DISP MTK_M4U_DOM_ID(11, 25)
/linux/lib/crypto/powerpc/
H A Dsha256-spe-asm.S101 #define R_LOAD_W(a, b, c, d, e, f, g, h, w, off) \ argument
105 rotrwi rT2,e,25; /* 1: S1" = e rotr 25 */ \
109 andc rT1,g,e; /* 1: ch' = ~e and g */ \
132 rotrwi rT2,d,25; /* 2: S1" = e rotr 25 */ \
136 andc rT1,f,d; /* 2: ch' = ~e and g */ \
139 add g,g,rT0; /* 2: temp1 = h + S1 */ \
142 add g,g,rT3; /* 2: temp1 = temp1 + temp1' */ \
144 add g,g,rT2; /* 2: temp1 = temp1 + K */ \
151 add c,c,g; /* 2: d = d + temp1 */ \
154 add g,g,rT3 /* 2: h = temp1 + temp2 */
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dselection.svg54 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
57 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
60 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
63 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
108 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
186 …lacementMap in="SourceGraphic" in2="result0" scale="62" xChannelSelector="B" yChannelSelector="G"/>
306 …-1.76-.163-5.531.25-3.542.39-9.008 1.21-10.281 1.876-1.6-.295-3.887-.507-5.875-.313-3.059.3-4.941.…
307 …3.86-.42-5.843-.188-3.052.358-4.945.568-6.875.781-.657.073-1.041.173-1.344.25-.427.128-.685.268-1.…
30925c1.133-.23 2.304.209 6.343-.5 4.04-.709 5.5-.927 6.22-1.187.715-.26 1.704-.568 2.343-1.094 1.924…
310 …56 2.266-.63 3.032-.874.24-.088.463-.122.75-.156 1.148-.14 2.316.34 6.375-.25 4.058-.59 5.562-.778…
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Dfexit_many_args.c12 int g, int ret) in BPF_PROG() argument
15 e == (void *)20 && f == 21 && g == 22 && ret == 133; in BPF_PROG()
22 int g, unsigned int h, long i, __u64 j, unsigned long k, in BPF_PROG() argument
26 e == (void *)20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
27 i == 24 && j == 25 && k == 26 && ret == 231; in BPF_PROG()
34 __u64 g, __u64 h, __u64 i, __u64 j, __u64 k, __u64 ret) in BPF_PROG() argument
37 e == 20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
38 i == 24 && j == 25 && k == 26 && ret == 231; in BPF_PROG()
H A Dfentry_many_args.c12 int g) in BPF_PROG() argument
15 e == (void *)20 && f == 21 && g == 22; in BPF_PROG()
22 int g, unsigned int h, long i, __u64 j, unsigned long k) in BPF_PROG() argument
25 e == (void *)20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
26 i == 24 && j == 25 && k == 26; in BPF_PROG()
33 __u64 g, __u64 h, __u64 i, __u64 j, __u64 k) in BPF_PROG() argument
36 e == 20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
37 i == 24 && j == 25 && k == 26; in BPF_PROG()
/linux/Documentation/devicetree/bindings/iio/accel/
H A Dadi,adxl380.yaml16 The ADXL380 and ADXL318 support the ±4 g, ±8 g, and ±16 g ranges,
17 while the ADXL382 and ADXL319 support ±15 g, ±30 g, and ±60 g ranges.
74 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
92 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
H A Dadi,adxl367.yaml17 data rates. Measurement ranges of +-2g, +-4g, and +-8g are available,
18 with a resolution of 0.25mg/LSB on the +-2 g range.
63 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
78 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
H A Dadi,adxl372.yaml7 title: Analog Devices ADXL371/ADXL372 3-Axis, +/-(200g) Digital Accelerometer
15 Analog Devices ADXL371/ADXL372 3-Axis, +/-(200g) Digital Accelerometer that
54 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
68 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
/linux/drivers/infiniband/hw/hfi1/
H A Dmad.h403 * get_link_speed - determine whether 12.5G or 25G speed
405 * @return: Return 2 if link speed identified as 12.5G
406 * or return 1 if link speed is 25G.
410 * speed is 25G, the function return as 1 as it is required
411 * by xmit counter conversion formula :-( 25G / link_speed).
413 * link speed is 25G or 2 if 12.5G.This is done to avoid
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_port.c63 DUPLEX_FULL : DUPLEX_UNKNOWN; // 1G HDX not supported in decode_cl37_word()
446 /* 12: Disable 5G/10G/25 BaseR PCS */ in sparx5_port_disable()
453 /* Disable 25G PCS */ in sparx5_port_disable()
459 /* 12: Disable 1G PCS */ in sparx5_port_disable()
731 * For BaseR, the serdes driver supports 10GGBASE-R and speed 5G/10G/25G in sparx5_serdes_set()
818 /* SFI : No in-band-aneg. Speeds 5G/10G/25G */ in sparx5_port_pcs_high_set()
823 /* Enable PCS for 25G device, speed 25G */ in sparx5_port_pcs_high_set()
829 /* Enable PCS for 5G/10G/25G devices, speed 5G/10G */ in sparx5_port_pcs_high_set()
836 /* Enable 5G/10G/25G MAC module */ in sparx5_port_pcs_high_set()
859 /* Switch between 1G/2500 and 5G/10G/25G devices */
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-oxp8 (usually 15W and 25W). By setting this attribute to 1, this
20 Some OneXPlayer devices (e.g., X1 series) feature a little LED
22 device is in the higher TDP mode (e.g., 25W). Once tt_toggle
H A Dsysfs-bus-dfl-devices-n3000-nios5 Description: Read-only. Returns the FEC mode of the 25G links of the
10 configured to 25G.
/linux/lib/crypto/
H A Dcurve25519-fiat32.c20 * fe limbs are bounded by 1.125*2^26,1.125*2^25,1.125*2^26,1.125*2^25,etc.
25 /* fe_loose limbs are bounded by 3.375*2^26,3.375*2^25,3.375*2^26,3.375*2^25,etc
42 h[1] = (a0>>26) | ((a1&((1<<19)-1))<< 6); /* (32-26) + 19 = 6+19 = 25 */ in fe_frombytes_impl()
44 h[3] = (a2>>13) | ((a3&((1<< 6)-1))<<19); /* (32-13) + 6 = 19+ 6 = 25 */ in fe_frombytes_impl()
46 h[5] = a4&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
47 h[6] = (a4>>25) | ((a5&((1<<19)-1))<< 7); /* (32-25) + 19 = 7+19 = 26 */ in fe_frombytes_impl()
48 h[7] = (a5>>19) | ((a6&((1<<12)-1))<<13); /* (32-19) + 12 = 13+12 = 25 */ in fe_frombytes_impl()
50 h[9] = (a7>> 6)&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
61 /* This function extracts 25 bits of result and 1 bit of carry in addcarryx_u25()
65 *low = x & ((1 << 25) - 1); in addcarryx_u25()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml23 IPv6 (S,G) multicast groups.
31 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
233 /* Then the 25G interfaces */
/linux/drivers/eisa/
H A Deisa.ids26 ACR1201 "Acer 1200 486/25 EISA System Board"
64 AIR0101 "AIR486SE/25/33 EISA Baby AT-foot print motherboard."
65 AIR0103 "AIR486SE/25/33/50"
66 AIR0201 "AIR486LE/25/33/50"
139 CCI1001 "Cache Computers Inc. 486/25 EISA System Board"
209 CPQ1201 "Compaq DESKPRO 486/25"
275 CPQ9005 "Compaq 386/25 Processor Board"
282 CPQ9034 "Compaq 486SX/25 Processor Board"
284 CPQ9036 "Compaq 486SX/25 Processor Board (8 MB)"
352 CPQ9903 "Compaq 486SX/25 Processor Board"
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.h45 #define AR9300_ANT_16S 25
50 #define AR9300_PAPRD_SCALE_1_S 25
67 * (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
295 * BIT 2/3 - MinCCApwr enable 2g/5g.
/linux/Documentation/filesystems/
H A Dzonefs.rst12 device support (e.g. f2fs), zonefs does not hide the sequential write
150 must be used. This type of elevator (e.g. mq-deadline) is set by default
177 devices, e.g. due to bad sectors. However, in addition to such known I/O
210 completed writes when the device write cache is flushed, e.g. on fsync().
339 A zoned block device (e.g. an NVMe Zoned Namespace device) may have limits on
413 dr-xr-xr-x 2 root root 1 Nov 25 13:23 cnv
414 dr-xr-xr-x 2 root root 55356 Nov 25 13:23 seq
423 -rw-r----- 1 root root 140391743488 Nov 25 13:23 0
435 -rw-r----- 1 root root 0 Nov 25 13:23 0
436 -rw-r----- 1 root root 0 Nov 25 13:23 1
[all …]
/linux/drivers/phy/microchip/
H A DKconfig13 Enable this for support of the 10G/25G SerDes on Microchip Sparx5.

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