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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
34 - Nipun Gupta <nipun.gupta@amd.com>
35 - Nikhil Agarwal <nikhil.agarwal@amd.com>
[all …]
/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.aggencoding.d.out3 value ------------- Distribution ------------- count
254 250 |█████████████████████████████▋ 250
263 259 |██████████████████████████████▊ 259
386 382 |██████████████████████████████▊ 259
395 391 |█████████████████████████████▋ 250
/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dmt6797-pinfunc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <dt-bindings/pinctrl/mt65xx.h>
1279 #define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
1280 #define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1)
1281 #define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2)
1282 #define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3)
1283 #define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6)
1284 #define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7)
1345 #define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0)
1346 #define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1)
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Drk3399-cru.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
198 #define ACLK_GIC 250
207 #define ACLK_ADB400M_PD_CORE_B 259
338 /* pmu-clocks indices */
379 /* soft-reset indices */
630 #define SRST_C_DP_CTRL 250
639 #define SRST_DPTX_SPDIF_REC 259
712 /* pmu soft-reset indices */
H A Dqcom,gcc-ipq806x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
252 #define PCIE_1_AUX_CLK 250
261 #define PCIE_2_ALT_REF_SRC 259
H A Dimx6qdl-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
260 #define IMX6QDL_CLK_PRE0 250
269 #define IMX6QDL_CLK_MLB_SEL 259
H A Dimx6sx-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
259 #define IMX6SX_CLK_PLL1 250
268 #define IMX6SX_PLL3_BYPASS 259
H A Dqcom,gcc-mdm9615.h1 /* SPDX-License-Identifier: GPL-2.0-only */
260 #define GP2_SRC 250
269 #define EBI1_CH0_CA_CLK 259
H A Dqcom,gcc-msm8960.h1 /* SPDX-License-Identifier: GPL-2.0-only */
258 #define GP2_SRC 250
267 #define EBI1_CH0_CA_CLK 259
H A Dqcom,gcc-msm8974.h1 /* SPDX-License-Identifier: GPL-2.0-only */
259 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250
268 #define GCC_USB2B_PHY_SLEEP_CLK 259
H A Drk3568-cru.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
10 /* pmucru-clocks indices */
67 /* cru-clocks indices */
314 #define DCLK_EBC 250
323 #define ACLK_RKVENC 259
488 /* pmu soft-reset indices */
504 /* soft-reset indices */
716 #define SRST_I_VICAP 250
726 #define SRST_A_VOP_NIU 259
H A Dqcom,gcc-apq8084.h1 /* SPDX-License-Identifier: GPL-2.0-only */
259 #define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
268 #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
H A Dpx30-cru.h1 /* SPDX-License-Identifier: GPL-2.0 */
126 #define HCLK_ISP 250
135 #define HCLK_HOST 259
178 /* pmu-clocks indices */
196 /* soft-reset indices */
H A Dtegra124-car-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides constants for binding nvidia,tegra124-car or
4 * nvidia,tegra132-car.
279 /* 250 */
289 #define TEGRA124_CLK_SCLK 259
H A Dtegra114-car.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides constants for binding nvidia,tegra114-car.
280 /* 250 */
290 #define TEGRA114_CLK_SCLK 259
H A Dimx8mp-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
255 #define IMX8MP_CLK_TRACE_ROOT 250
264 #define IMX8MP_CLK_WDOG1_ROOT 259
H A Dimx8mq-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
382 #define IMX8MQ_CLK_OCOTP_ROOT 250
397 #define IMX8MQ_CLK_GPIO1_ROOT 259
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91sam9261ek.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 /dts-v1/;
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <18432000>;
40 atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
44 bits-per-pixel = <16>;
45 atmel,lcdcon-backlight;
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/arm/
H A Dqcom,ids.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
12 * older chipsets (qcom,msm-id) and in socinfo driver:
112 #define QCOM_ID_MSM8616 250
117 #define QCOM_ID_MSM8208 259
284 * DTS for older chipsets (qcom,board-id):
/freebsd/sys/amd64/linux/
H A Dlinux_syscall.h4 * DO NOT EDIT-- this file is automatically @generated.
242 #define LINUX_SYS_linux_keyctl 250
251 #define LINUX_SYS_linux_mknodat 259
/freebsd/crypto/openssl/include/openssl/
H A Dsslerr.h3 * Copyright 1995-2024 The OpenSSL Project Authors. All Rights Reserved.
320 # define SSL_R_UNKNOWN_KEY_EXCHANGE_TYPE 250
330 # define SSL_R_UNSUPPORTED_SSL_VERSION 259
/freebsd/sys/arm64/linux/
H A Dlinux_syscalls.c4 * DO NOT EDIT-- this file is automatically @generated.
258 "#250", /* 250 = unimpl_md_syscall */
267 "#259", /* 259 = unimpl_md_syscall */
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mp_ccm.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
302 #define IMX8MP_CLK_TRACE_ROOT 250
314 #define IMX8MP_CLK_WDOG1_ROOT 259
/freebsd/sys/amd64/linux32/
H A Dlinux32_syscall.h4 * DO NOT EDIT-- this file is automatically @generated.
223 #define LINUX32_SYS_linux_fadvise64 250
231 #define LINUX32_SYS_linux_timer_create 259
/freebsd/sys/i386/linux/
H A Dlinux_syscall.h4 * DO NOT EDIT-- this file is automatically @generated.
229 #define LINUX_SYS_linux_fadvise64 250
237 #define LINUX_SYS_linux_timer_create 259

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