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/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
151 /* Clock control and hardware workarounds (corerev >= 20) */
184 /* PMU registers (corerev >= 20) */
199 u32 gpiosel; /* 0x638, rev >= 1 */
200 u32 gpioenable; /* 0x63c, rev >= 1 */
226 #define CID_PKG_SHIFT 20 /* Package Option shift */
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
94 * Rev Fieldname Bits
119 * Rev Fieldname Bits
137 * Rev Fieldname Bits
158 * Rev Fieldname Bits
180 * Rev Fieldname Bits
199 * Rev Fieldname Bits
221 * Rev Fieldname Bits
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h16 #define BCMA_CC_ID_PKG_SHIFT 20
50 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
51 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
53 #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
57 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
91 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
92 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
110 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
132 #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
[all …]
H A Dbcma_driver_pci.h47 #define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
48 #define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
49 #define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
50 #define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
67 #define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
68 #define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
69 #define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
70 #define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
85 #define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
86 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
[all …]
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h22 #define SSB_CHIPCO_PACKSHIFT 20
53 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
54 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
59 #define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
88 #define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */
89 #define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */
90 #define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */
112 #define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */
113 #define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */
114 #define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_g.c41 5, -7, -20, -20,
42 -20, -20, -20, -20,
43 -20, -20, -20, -20,
73 /* APHY.rev < 5 || GPHY.rev < 6 */ in generate_rfatt_list()
90 /* Radio.rev == 8 && Radio.version == 0x2050 */ in generate_rfatt_list()
305 if (phy->rev <= 1) { in b43_set_all_gains()
311 if (phy->rev <= 1) in b43_set_all_gains()
335 if (phy->rev <= 1) { in b43_set_original_gains()
341 if (phy->rev <= 1) in b43_set_original_gains()
412 u16 backup[20] = { 0 }; in b43_calc_nrssi_offset()
[all …]
H A Dppr.c131 /* MCS 20 SISO */ in b43_ppr_load_max_from_sprom()
141 /* MCS 20 CDD */ in b43_ppr_load_max_from_sprom()
145 if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) in b43_ppr_load_max_from_sprom()
151 if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) in b43_ppr_load_max_from_sprom()
155 /* OFDM 20 CDD */ in b43_ppr_load_max_from_sprom()
165 /* MCS 20 STBC */ in b43_ppr_load_max_from_sprom()
169 if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) in b43_ppr_load_max_from_sprom()
175 if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) in b43_ppr_load_max_from_sprom()
179 /* MCS 20 SDM */ in b43_ppr_load_max_from_sprom()
H A Db43.h55 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
56 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
76 /* PIO on core rev < 11 */
85 /* PIO on core rev >= 11 */
93 #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */
94 #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */
125 #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */
126 #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */
127 #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */
128 #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */
[all …]
H A Dwa.c26 if (phy->rev <= 2) in b43_wa_initgains()
34 if (phy->rev <= 3) in b43_wa_initgains()
36 else if (phy->rev == 5) { in b43_wa_initgains()
40 if (phy->rev >= 3) in b43_wa_initgains()
48 if (0 /* FIXME: For APHY.rev=2 this might be needed */) { in b43_wa_rssi_lt()
87 if (phy->rev == 1) in b43_wa_nft()
117 if (phy->rev >= 6) { in b43_wa_nst()
159 if (phy->rev == 1) { in b43_wa_crs_ed()
161 } else if (phy->rev == 2) { in b43_wa_crs_ed()
192 if (dev->phy.rev == 1) { in b43_wa_wrssi_offset()
[all …]
/linux/drivers/bcma/
H A Ddriver_chipcommon.c43 WARN(bus->chipinfo.rev <= 1, "No watchdog available\n"); in bcma_core_cc_has_pmu_watchdog()
64 else if (cc->core->id.rev < 26) in bcma_chipco_watchdog_get_max_timer()
67 nb = (cc->core->id.rev >= 37) ? 32 : 24; in bcma_chipco_watchdog_get_max_timer()
120 bus->chipinfo.rev <= 1) { in bcma_chipco_watchdog_register()
160 if (cc->core->id.rev == 38 || in bcma_core_chipcommon_flash_detect()
178 if (cc->core->id.rev >= 11) in bcma_core_chipcommon_early_init()
181 if (cc->core->id.rev >= 35) in bcma_core_chipcommon_early_init()
203 if (cc->core->id.rev >= 20) { in bcma_core_chipcommon_init()
220 if (cc->core->id.rev >= 16) { in bcma_core_chipcommon_init()
351 if (cc->core->id.rev < 20) in bcma_chipco_gpio_pullup()
[all …]
/linux/drivers/acpi/
H A Dpci_mcfg.c42 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
46 #define AL_ECAM(table_id, rev, seg, ops) \ argument
47 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
86 #define THUNDER_PEM_QUIRK(rev, node) \ argument
87 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
89 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
91 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
93 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
95 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
97 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c142 if (phy->rev <= 1) { in b43legacy_set_all_gains()
178 if (phy->rev <= 1) { in b43legacy_set_original_gains()
256 if (j >= 20) in b43legacy_radio_aci_detect()
274 if (!((phy->type == B43legacy_PHYTYPE_G) && (phy->rev > 0))) in b43legacy_radio_aci_scan()
369 u16 backup[20] = { 0 }; in b43legacy_calc_nrssi_offset()
399 if (phy->rev >= 6) { in b43legacy_calc_nrssi_offset()
434 udelay(20); in b43legacy_calc_nrssi_offset()
490 udelay(20); in b43legacy_calc_nrssi_offset()
505 if (phy->rev >= 6) { in b43legacy_calc_nrssi_offset()
525 if (phy->rev >= 6) { in b43legacy_calc_nrssi_offset()
[all …]
H A Dphy.c65 5, -7, -20, -20,
66 -20, -20, -20, -20,
67 -20, -20, -20, -20,
123 if (phy->type == B43legacy_PHYTYPE_G && phy->rev == 1) { in b43legacy_phy_calibrate()
164 phy->rev >= 2 && in b43legacy_phy_init_pctl()
198 if (phy->rev == 1) in b43legacy_phy_agcsetup()
206 if (phy->rev == 1) { in b43legacy_phy_agcsetup()
236 if (phy->rev == 1) in b43legacy_phy_agcsetup()
260 if (phy->rev == 1) { in b43legacy_phy_agcsetup()
274 if (phy->rev > 2) { in b43legacy_phy_agcsetup()
[all …]
/linux/drivers/mtd/spi-nor/
H A Dsfdp.h22 /* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. */
23 #define BFPT_DWORD_MAX 20
40 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
55 * (from JESD216 rev B)
85 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
86 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
87 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
88 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
89 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
90 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dpinctrl-starfive-jh7100.h17 * | dout | doen | din | dout rev | doen rev | gpio nr |
22 * dout rev: output signal reverse bit
23 * doen rev: output enable signal reverse bit
64 #define GPO_I2SRX_MCLK_OUT 20
217 #define GPI_I2SRX_SDIN_BIT0 20
/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c8 * 7 - SDRAM auto-power-up failure (rev A0)
10 * SDRAM reads (rev A0, B0, B1)
12 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
33 const char name[20];
54 .trcd = 20,
55 .trp = 20,
63 .trcd = 20,
64 .trp = 20,
73 .trp = 20,
81 .trp = 20,
[all …]
/linux/drivers/usb/phy/
H A Dphy-omap-otg.c31 #define OMAP_OTG_ASESSVLD (1 << 20)
92 u32 rev; in omap_otg_probe() local
128 rev = readl(otg_dev->base); in omap_otg_probe()
131 "OMAP USB OTG controller rev %d.%d (%s, id=%d, vbus=%d)\n", in omap_otg_probe()
132 (rev >> 4) & 0xf, rev & 0xf, config->extcon, otg_dev->id, in omap_otg_probe()
/linux/sound/pci/echoaudio/
H A Dlayla20.c25 #define PX_DIGITAL_IN 20 /* 2 */
32 #define BX_DIGITAL_IN 20 /* 2 */
68 { PCI_DEVICE_SUB(0x1057, 0x1801, 0xECC0, 0x0030) }, /* DSP 56301 Layla20 rev.0 */
69 { PCI_DEVICE_SUB(0x1057, 0x1801, 0xECC0, 0x0031) }, /* DSP 56301 Layla20 rev.1 */
/linux/drivers/soc/tegra/fuse/
H A Dspeedo-tegra20.c14 #define CPU_SPEEDO_LSBIT 20
30 #define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2) argument
32 (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
/linux/arch/powerpc/kernel/
H A Dcpu_setup_6xx.S137 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
153 rlwinm r3,r3,0,20,31
160 rlwinm r3,r3,0,20,31
246 * it's known to be bogus on rev 2.1 and earlier
329 #define CS_ICTRL 20
399 /* If rev 2.x, backup HID2 */
489 * that is restore HID2 on rev 2.x and PLL config & switch
492 /* If rev 2.x, restore HID2 with low voltage bit cleared */
/linux/drivers/eisa/
H A Deisa.ids28 ACR1341 "M1 486SX/20 CPU Board"
29 ACR1351 "M1 486SX/20 CPU Board"
30 ACR1361 "M1 487/20 CPU Board"
31 ACR1371 "M1 487/20 CPU Board"
32 ACR1381 "M1 486/20 CPU Board"
33 ACR1391 "M1 486/20 CPU Board"
95 AMI15D1 "AMI SCSI Host Adapter - Rev 2"
509 ETI1001 "NE3300 Ethernet Rev. C & D"
522 GDT2001 "GDT2000/GDT2020 Fast-SCSI Cache Controller - Rev. 1.0"
523 GDT3001 "GDT3000/GDT3020 Dual Channel SCSI Controller - Rev. 1.0"
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
188 <&sdma 20>;
216 reg-names = "rev", "sysc";
256 reg-names = "rev", "sysc";
290 reg-names = "rev", "sysc";
318 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
322 reg-names = "rev", "sysc";
354 reg-names = "rev", "sysc";
385 reg-names = "rev", "sysc";
[all …]
H A Dam33xx.dtsi226 reg-names = "rev";
246 ti,edma-memcpy-channels = <20 21>;
254 reg-names = "rev", "sysc";
277 reg-names = "rev", "sysc";
300 reg-names = "rev", "sysc";
324 reg-names = "rev", "sysc", "syss";
351 reg-names = "rev", "sysc";
439 &cppi41dma 19 0 &cppi41dma 20 0
447 &cppi41dma 20 1 &cppi41dma 21 1
512 reg-names = "rev";
[all …]
/linux/arch/arm/mach-imx/
H A Dmach-imx6q.c159 (0xf << 16) | (0x7 << 20)); in imx6q_axi_init()
163 (0xf << 16) | (0x7 << 20)); in imx6q_axi_init()
173 * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. in imx6q_init_machine()
175 * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. in imx6q_init_machine()
/linux/drivers/net/ethernet/sfc/
H A Def100_regs.h18 * E<type>_<min-rev><max-rev>_
28 * <min-rev> is the first revision to which the definition applies:
33 * then <max-rev> is the last revision to which the definition applies;
171 #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20
257 #define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20
261 #define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20
278 #define ESF_GZ_VSEC_LEN_LBN 20
458 #define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20

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