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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml80 description: Supported slew rate based on Fmax values (MHz)
81 enum: [83, 133, 150, 166, 208]
113 slew-rate = <208>;
119 slew-rate = <208>;
/freebsd/sys/net80211/
H A Dieee80211_regdomain.h94 CTRY_DENMARK = 208, /* Denmark */
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.
H A Dieee80211_ht.c66 { 208, 231, 432, 480 }, /* MCS 13 */
80 { 208, 231, 432, 480 }, /* MCS 27 */
98 { 208, 231, 432, 480 }, /* MCS 45 */
111 { 208, 231, 432, 480 }, /* MCS 58 */
113 { 208, 231, 432, 480 }, /* MCS 60 */
396 ic_printf(ic, "%s MCS 20MHz\n", modestr); in ht_announce()
399 ic_printf(ic, "%s MCS 20MHz SGI\n", modestr); in ht_announce()
403 ic_printf(ic, "%s MCS 40MHz:\n", modestr); in ht_announce()
408 ic_printf(ic, "%s MCS 40MHz SGI:\n", modestr); in ht_announce()
1978 /* 20 Mhz */ in ieee80211_vht_get_vhtflags()
[all …]
H A Dieee80211.h798 #define IEEE80211_HTCAP_SHORTGI20 0x0020 /* Short GI in 20MHz */
799 #define IEEE80211_HTCAP_SHORTGI40 0x0040 /* Short GI in 40MHz */
810 #define IEEE80211_HTCAP_DSSSCCK40 0x1000 /* DSSS/CCK in 40MHz */
812 #define IEEE80211_HTCAP_40INTOLERANT 0x4000 /* 40MHz intolerant */
877 #define IEEE80211_HTINFO_TXWIDTH_20 0x00 /* 20MHz width */
963 IEEE80211_VHT_CHANWIDTH_USE_HT = 0, /* 20 MHz or 40 MHz */
964 IEEE80211_VHT_CHANWIDTH_80MHZ = 1, /* 80MHz */
965 IEEE80211_VHT_CHANWIDTH_160MHZ = 2, /* 160MHz (deprecated) */
966 IEEE80211_VHT_CHANWIDTH_80P80MHZ = 3, /* 80+80MHz (deprecated) */
1081 * 0 - 20 MHz
[all …]
H A Dieee80211_phy.c571 26, 52, 78, 104, 156, 208, 234, 260,
572 52, 104, 156, 208, 312, 416, 468, 520,
574 104, 208, 312, 416, 624, 832, 936, 1040
719 * (VHT-MCSs for Mandatory 20 MHZ, Nss=1).
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam5729-beagleboneai.dts422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
555 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
556 /* HS: High speed up to 50 MHz (3.3 V signaling). */
557 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
558 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
559 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
560 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
561 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmmc-controller.yaml93 - for eMMC, the maximum supported frequency is 200MHz,
95 frequency of 208MHz,
97 384MHz.
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dgcw0.dts124 144 160 176 192 208 224 240 255>;
444 * We use a rate of 432 MHz, which is the least common multiple of
445 * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
478 * 750 kHz for the system timer and clocksource, 12 MHz for the OST,
/freebsd/sys/dev/ath/
H A Dif_ath_tx_ht.c174 /* 20MHz 40MHz */
180 { 208, 432 }, // 5: 64-QAM 2/3
186 { 208, 432 }, // 11: 16-QAM 1/2
200 { 208, 432 }, // 25: QPSK 1/2
476 * whether high rate is 20 or 40Mhz and half or full GI. in ath_compute_num_delims()
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.c353 .freq = 4920, /* MHz */
361 .freq = 4930, /* MHz */
369 .freq = 4940, /* MHz */
377 .freq = 4950, /* MHz */
385 .freq = 4960, /* MHz */
393 .freq = 4970, /* MHz */
401 .freq = 4980, /* MHz */
409 .freq = 4990, /* MHz */
417 .freq = 5000, /* MHz */
425 .freq = 5010, /* MHz */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,rz-mtu3.yaml20 - Operating frequency Up to 100 MHz
283 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra186-clock.h644 #define TEGRA186_CLK_AON_CPU_NIC 208
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7790.dtsi82 capacity-dmips-mhz = <1024>;
104 capacity-dmips-mhz = <1024>;
126 capacity-dmips-mhz = <1024>;
148 capacity-dmips-mhz = <1024>;
170 capacity-dmips-mhz = <539>;
182 capacity-dmips-mhz = <539>;
194 capacity-dmips-mhz = <539>;
206 capacity-dmips-mhz = <539>;
789 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1066 clocks = <&cpg CPG_MOD 208>;
[all …]
H A Dr8a7742.dtsi60 capacity-dmips-mhz = <1024>;
82 capacity-dmips-mhz = <1024>;
104 capacity-dmips-mhz = <1024>;
126 capacity-dmips-mhz = <1024>;
757 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1031 clocks = <&cpg CPG_MOD 208>;
1036 resets = <&cpg 208>;
/freebsd/sys/dev/ath/ath_hal/
H A Dah.c387 26, 52, 78, 104, 156, 208, 234, 260,
388 52, 104, 156, 208, 312, 416, 468, 520,
390 104, 208, 312, 416, 624, 832, 936, 1040
569 * Maybe AR5211 has separate 11b and 11g only modes, so 11b is 22MHz
570 * and 11g is 44MHz, but AR5416 and later run 11b in 11bg mode, right?
1541 * Do a 2GHz specific MHz->IEEE based on the hardware
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8976.dtsi40 capacity-dmips-mhz = <573>;
51 capacity-dmips-mhz = <573>;
62 capacity-dmips-mhz = <573>;
73 capacity-dmips-mhz = <573>;
84 capacity-dmips-mhz = <1024>;
95 capacity-dmips-mhz = <1024>;
106 capacity-dmips-mhz = <1024>;
117 capacity-dmips-mhz = <1024>;
674 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
H A Dmsm8953.dtsi46 capacity-dmips-mhz = <1024>;
56 capacity-dmips-mhz = <1024>;
66 capacity-dmips-mhz = <1024>;
76 capacity-dmips-mhz = <1024>;
86 capacity-dmips-mhz = <1024>;
96 capacity-dmips-mhz = <1024>;
106 capacity-dmips-mhz = <1024>;
116 capacity-dmips-mhz = <1024>;
492 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1126 * sdm632, the max for sdm450 is 600MHz.
H A Dsdm670.dtsi40 capacity-dmips-mhz = <610>;
67 capacity-dmips-mhz = <610>;
89 capacity-dmips-mhz = <610>;
111 capacity-dmips-mhz = <610>;
133 capacity-dmips-mhz = <610>;
155 capacity-dmips-mhz = <610>;
177 capacity-dmips-mhz = <1024>;
199 capacity-dmips-mhz = <1024>;
1163 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
H A Dsdm630.dtsi62 capacity-dmips-mhz = <1126>;
82 capacity-dmips-mhz = <1126>;
97 capacity-dmips-mhz = <1126>;
112 capacity-dmips-mhz = <1126>;
127 capacity-dmips-mhz = <1024>;
147 capacity-dmips-mhz = <1024>;
162 capacity-dmips-mhz = <1024>;
177 capacity-dmips-mhz = <1024>;
724 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/dev/ichiic/
H A Dig4_iic.c93 .ic_clock_rate = 100, /* MHz */
96 .ic_clock_rate = 100, /* MHz */
116 .scl_fall_time = 208,
126 .scl_fall_time = 208,
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a774e1.dtsi138 capacity-dmips-mhz = <1024>;
152 capacity-dmips-mhz = <1024>;
166 capacity-dmips-mhz = <1024>;
180 capacity-dmips-mhz = <1024>;
196 capacity-dmips-mhz = <535>;
209 capacity-dmips-mhz = <535>;
222 capacity-dmips-mhz = <535>;
235 capacity-dmips-mhz = <535>;
967 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1530 clocks = <&cpg CPG_MOD 208>;
[all …]
H A Dr8a774a1.dtsi131 capacity-dmips-mhz = <1024>;
144 capacity-dmips-mhz = <1024>;
159 capacity-dmips-mhz = <560>;
171 capacity-dmips-mhz = <560>;
183 capacity-dmips-mhz = <560>;
195 capacity-dmips-mhz = <560>;
903 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1418 clocks = <&cpg CPG_MOD 208>;
1422 resets = <&cpg 208>;
H A Dr8a77961.dtsi153 capacity-dmips-mhz = <1024>;
167 capacity-dmips-mhz = <1024>;
183 capacity-dmips-mhz = <535>;
196 capacity-dmips-mhz = <535>;
209 capacity-dmips-mhz = <535>;
222 capacity-dmips-mhz = <535>;
946 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1488 clocks = <&cpg CPG_MOD 208>;
1492 resets = <&cpg 208>;
H A Dr8a77951.dtsi153 capacity-dmips-mhz = <1024>;
167 capacity-dmips-mhz = <1024>;
181 capacity-dmips-mhz = <1024>;
195 capacity-dmips-mhz = <1024>;
211 capacity-dmips-mhz = <535>;
224 capacity-dmips-mhz = <535>;
237 capacity-dmips-mhz = <535>;
250 capacity-dmips-mhz = <535>;
1027 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1617 clocks = <&cpg CPG_MOD 208>;
[all …]
H A Dr8a77960.dtsi153 capacity-dmips-mhz = <1024>;
167 capacity-dmips-mhz = <1024>;
183 capacity-dmips-mhz = <535>;
196 capacity-dmips-mhz = <535>;
209 capacity-dmips-mhz = <535>;
222 capacity-dmips-mhz = <535>;
946 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1488 clocks = <&cpg CPG_MOD 208>;
1492 resets = <&cpg 208>;

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