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/linux/drivers/video/fbdev/kyro/
H A DSTG4000OverlayDevice.c36 #define STG4000_OVRL_ALIGN 2
57 /*clipped on-screen pixel position of overlay */
63 /*clipped pixel pos of source data within buffer thses need to be 128 bit word aligned */
69 /* on-screen pixel position of overlay */
152 return -EINVAL; in CreateOverlaySurface()
155 /* Stride in 16 byte words - 16Bpp */ in CreateOverlaySurface()
190 (inWidth & 0x1) ? (inWidth + 1 / 2) : (inWidth / 2); in CreateOverlaySurface()
202 /* Align U,V data to 32byte boundary */ in CreateOverlaySurface()
211 ulOffset += (inHeight / 2) * (uvStride * 16); in CreateOverlaySurface()
212 /* Align U,V data to 32byte boundary */ in CreateOverlaySurface()
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/linux/include/video/
H A Dudlfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * DisplayLink X server as yet - need both to be modified in tandem
59 /* blit-only rendering path metrics, exposed through sysfs */
60 atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */
63 atomic_t cpu_kcycles_used; /* transpired during pixel processing */
71 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
73 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
79 #define FREE_URB_TIMEOUT (HZ*2)
81 #define BPP 2
93 #define MIN_RAW_PIX_BYTES 2
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - enum:
25 - mediatek,mt8188-disp-padding
26 - mediatek,mt8195-mdp3-padding
27 - items:
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_hevc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/v4l2-mem2mem.h>
14 #define VERT_FILTER_RAM_SIZE 8 /* bytes per pixel row */
19 #define BSD_CTRL_RAM_SIZE 4 /* bytes per pixel row */
21 #define VERT_SAO_RAM_SIZE 48 /* bytes per pixel */
35 struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; in hantro_hevc_ref_init()
37 hevc_dec->ref_bufs_used = 0; in hantro_hevc_ref_init()
43 struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; in hantro_hevc_get_ref_buf()
48 if (hevc_dec->ref_bufs_poc[i] == poc) { in hantro_hevc_get_ref_buf()
49 hevc_dec->ref_bufs_used |= 1 << i; in hantro_hevc_get_ref_buf()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_osd_afbcd.c1 // SPDX-License-Identifier: GPL-2.0+
26 * for the 2 OSD planes.
30 * - basic AFBC buffer for RGB32 only, thus YTR feature is mandatory
31 * - SPARSE layout and SPLIT layout
32 * - only 16x16 superblock
35 * decoded pixel stream to the OSD1 Plane pixel composer.
43 * - basic AFBC buffer for multiple RGB and YUV pixel formats
44 * - SPARSE layout and SPLIT layout
45 * - 16x16 and 32x8 "wideblk" superblocks
46 * - Tiled header
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/linux/Documentation/admin-guide/media/
H A Draspberrypi-pisp-be.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Raspberry Pi PiSP Back End Memory-to-Memory ISP (pisp-be)
10 The PiSP Back End is a memory-to-memory Image Signal Processor (ISP) which reads
13 pixel data back to memory through two distinct output channels.
19 tessellation and the computation of low-level configuration parameters is
24 an image sensor through a MIPI CSI-2 compatible capture interface, storing them
29 The pisp-be driver
32 The Raspberry Pi PiSP Back End (pisp-be) driver is located under
33 drivers/media/platform/raspberrypi/pisp-be. It uses the `V4L2 API` to register
38 The media topology registered by the `pisp-be` driver is represented below:
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H A Dstarfive_camss.rst1 .. SPDX-License-Identifier: GPL-2.0
10 ------------
24 ----------------------------------
28 |\ +---------------+ +-----------+
29 +----------+ | \ | | | |
31 | MIPI |----->| |----->| ISP |----->| |
33 +----------+ | | | | | Memory |
34 |MUX| +---------------+ | Interface |
35 +----------+ | | | |
36 | | | |---------------------------->| |
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H A Dqcom_camss.rst1 .. SPDX-License-Identifier: GPL-2.0
9 ------------
25 ----------------------------------
30 - 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
32 - 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
36 - ISPIF (ISP Interface) module. Handles the routing of the data streams from
38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
39 hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input
48 -----------------------
52 - Input from camera sensor via CSIPHY;
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/linux/Documentation/userspace-api/media/v4l/
H A Dcrop.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 Image Cropping, Insertion and Scaling -- the CROP API
12 <selection-api>`. The new API should be preferred in most cases,
13 with the exception of pixel aspect ratio detection, which is
15 equivalent in the SELECTION API. See :ref:`selection-vs-crop` for a
62 .. _crop-scale:
64 .. kernel-figure:: crop.svg
66 :align: center
81 :ref:`vbi-hsync`). Vertically ITU-R line numbers of the first field
82 (see ITU R-525 line numbering for :ref:`525 lines <vbi-525>` and for
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/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fh.h>
17 #include <media/v4l2-ctrls.h>
19 #define S5P_JPEG_M2M_NAME "s5p-jpeg"
43 #define SJPEG_FMT_FLAG_DEC_CAPTURE (1 << 2)
53 #define S5P_JPEG_DISABLE -1
95 * struct s5p_jpeg - JPEG IP abstraction
142 * struct s5p_jpeg_fmt - driver's internal color format data
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/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
23 struct clk *clk_di_pixel; /* resulting pixel clock */
47 DI_PIN13 = 2,
61 DI_SYNC_INT_HSYNC = 2,
66 DI_SYNC_CNT1 = 2, /* counter >= 2 only */
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispresizer.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
37 #define MIN_OUT_HEIGHT 2
42 * "TRM ES3.1, table 12-46"
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
75 /* For 8-phase 4-tap vertical filter: */
86 /* For 4-phase 7-tap horizontal filter: */
94 /* For 4-phase 7-tap vertical filter: */
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/linux/drivers/gpu/drm/imx/ipuv3/
H A Dipuv3-crtc.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/dma-mapping.h>
17 #include <video/imx-ipu-v3.h>
26 #include "imx-drm.h"
27 #include "ipuv3-plane.h"
36 struct ipu_plane *plane[2];
53 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); in ipu_crtc_atomic_enable()
57 ipu_dc_enable_channel(ipu_crtc->dc); in ipu_crtc_atomic_enable()
58 ipu_di_enable(ipu_crtc->di); in ipu_crtc_atomic_enable()
69 if (plane == &ipu_crtc->plane[0]->base) in ipu_crtc_disable_planes()
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/linux/drivers/video/fbdev/
H A Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
116 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
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H A Dtgafb.c2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
37 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
118 return tgafb_register(&pdev->dev); in tgafb_pci_register()
123 tgafb_unregister(&pdev->dev); in tgafb_pci_unregister()
135 { "DEC ", "PMAGD-AA" },
169 * tgafb_check_var - Optional function. Validates a var passed in.
176 struct tga_par *par = (struct tga_par *)info->par; in tgafb_check_var()
178 if (!var->pixclock) in tgafb_check_var()
179 return -EINVAL; in tgafb_check_var()
181 if (par->tga_type == TGA_TYPE_8PLANE) { in tgafb_check_var()
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H A Dpxafb.c5 * Copyright (C) 2004 Jean-Frederic Clere.
21 * linux-arm-kernel@lists.arm.linux.org.uk
31 * Copyright (C) 2006-2008 Marvell International Ltd.
50 #include <linux/dma-mapping.h>
68 #include <linux/platform_data/video-pxafb.h>
76 #include "pxa3xx-regs.h"
99 return __raw_readl(fbi->mmio_base + off); in lcd_readl()
105 __raw_writel(val, fbi->mmio_base + off); in lcd_writel()
119 * 2. When we are blanking, but immediately unblank before in pxafb_schedule_work()
123 if (fbi->task_state == C_ENABLE && state == C_REENABLE) in pxafb_schedule_work()
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/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.c34 mcif_wb30->mcif_wb_regs->reg
37 mcif_wb30->base.ctx
41 mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
52 * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10
54 * unsigned int time_per_pixel; // time per pixel, in ns
55 * unsigned int arbitration_slice; // 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes
66 * 2. configure wbif register
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub32_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub32_warmup_mcif()
86 // REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid); in mmhubbub32_warmup_mcif()
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/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.c34 mcif_wb30->mcif_wb_regs->reg
37 mcif_wb30->base.ctx
41 mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
52 * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10
54 * unsigned int time_per_pixel; // time per pixel, in ns
55 * unsigned int arbitration_slice; // 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes
66 * 2. configure wbif register
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub3_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub3_warmup_mcif()
86 // REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid); in mmhubbub3_warmup_mcif()
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/linux/drivers/media/test-drivers/vimc/
H A Dvimc-scaler.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * vimc-scaler.c Virtual Media Controller Driver
5 * Copyright (C) 2015-2017 Helen Koike <helen.fornazier@gmail.com>
11 #include <linux/v4l2-mediabus.h>
12 #include <media/v4l2-rect.h>
13 #include <media/v4l2-subdev.h>
15 #include "vimc-common.h"
29 struct media_pad pads[2];
74 .width = sink_fmt->width, in vimc_scaler_get_crop_bound_sink()
75 .height = sink_fmt->height, in vimc_scaler_get_crop_bound_sink()
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_client.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
41 * value of 2GB. This is far more than any current applications use.
66 /* Disable pixel merging for this render. */
77 #define ROGUE_COMPUTE_FLAG_PREVENT_ALL_OVERLAP BIT_MASK(2)
209 /* All values below the ALIGN(8) must be 64 bit. */
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
320 * single RGXFW_ALIGN to align all the 64 bit values in the second section.
/linux/drivers/staging/media/tegra-video/
H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
64 /* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
86 #define CSI_PP_SINGLE_SHOT_ENABLE (0x1 << 2)
117 #define PG_MODE_OFFSET 2
150 writel_relaxed(val, chan->vi->iomem + addr); in tegra_vi_write()
155 return readl_relaxed(chan->vi->iomem + addr); in tegra_vi_read()
164 vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); in vi_csi_write()
174 vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); in vi_csi_read()
185 struct tegra_vi *vi = chan->vi; in tegra210_channel_host1x_syncpt_init()
191 for (i = 0; i < chan->numgangports; i++) { in tegra210_channel_host1x_syncpt_init()
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/linux/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_kms.c1 // SPDX-License-Identifier: GPL-2.0+
33 /* -----------------------------------------------------------------------------
101 .hsub = 2,
106 .hsub = 2,
111 .hsub = 2,
115 .planes = 2,
116 .hsub = 2,
120 .planes = 2,
121 .hsub = 2,
125 .planes = 2,
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/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
72 #define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
85 #define LANEENABLE_L1EN BIT(2)
87 #define LANEENABLE_L3EN BIT(2)
108 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_kms.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Mode Setting
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
22 #include <linux/dma-buf.h>
37 /* -----------------------------------------------------------------------------
86 .hsub = 2,
94 .hsub = 2,
101 .planes = 2,
102 .hsub = 2,
109 .planes = 2,
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/linux/drivers/media/platform/st/sti/hva/
H A Dhva-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "hva-hw.h"
26 #define SEARCH_WINDOW_BUFFER_MAX_SIZE(w) ((4 * MB_W(w) + 42) * 256 * 3 / 2)
32 /* source buffer copy in YUV 420 MB-tiled format with size=16*256*3/2 */
33 #define CURRENT_WINDOW_BUFFER_MAX_SIZE (16 * 256 * 3 / 2)
37 * for deblocking with size=4*16*MBx*2
39 #define LOCAL_RECONSTRUCTED_BUFFER_MAX_SIZE(w) (4 * 16 * MB_W(w) * 2)
60 {V4L2_MPEG_VIDEO_H264_LEVEL_1_0, 1485, 99, 64, 175, 2},
61 {V4L2_MPEG_VIDEO_H264_LEVEL_1B, 1485, 99, 128, 350, 2},
62 {V4L2_MPEG_VIDEO_H264_LEVEL_1_1, 3000, 396, 192, 500, 2},
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