Home
last modified time | relevance | path

Searched +full:2 +full:- +full:49 (Results 1 – 25 of 1113) sorted by relevance

12345678910>>...45

/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = base.KernelModule("hid-multitouch", "hid_multitouch")
30 "CYPRESS": BIT(2),
109 input_info=(BusType.USB, 1, 2), argument
222 elif value == 2:
310 Unit Exponent (-1)
335 Unit Exponent (-4)
346 Report ID (2)
378 Unit Exponent (-1)
[all …]
H A Dtest_tablet.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
44 https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/windows-pen-states
67 def from_evdev(cls, evdev, test_button) -> "PenState":
85 raise ValueError("2 tools are not allowed")
100 ) -> "PenState":
147 def valid_transitions(self) -> Tuple["PenState", ...]:
207 def historically_tolerated_transitions(self) -> Tuple["PenState", ...]:
209 for skipping the in-range state, due to historical reasons.
272 def legal_transitions() -> Dict[str, Tuple["PenState", ...]]:
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-address.h7 * Copyright (c) 2003-2009 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
38 CVMX_MIPS_SPACE_XKPHYS = 2LL,
47 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
56 CVMX_ADD_WIN_UNUSED = 2L,
71 CVMX_ADD_WIN_DMA_SENDDMA = 2L,
76 /* send out a single-tick command on the NCB bus */
84 * Octeon-I HW never interprets this X (<39:36> reserved
[all …]
/linux/include/dt-bindings/clock/
H A Dgoogle,gs101.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
14 #define CLK_FOUT_SHARED1_PLL 2
63 #define CLK_MOUT_CMU_HSI1_BUS 49
245 #define CLK_MOUT_APM_FUNCSRC 2
292 #define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 49
318 #define CLK_MOUT_PLL_USB 2
365 #define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49
372 #define CLK_MOUT_HSI2_MMC_CARD_USER 2
419 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
434 #define CLK_MOUT_MISC_SSS_USER 2
[all …]
H A Dspacemit,k1-syscon.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
3 * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
12 #define CLK_PLL3 2
49 #define CLK_PLL1_61P44 2
91 #define CLK_UART3 2
138 #define CLK_IPC_AP2AUD 49
195 #define RESET_UART3 2
242 #define RESET_IPC_AP2AUD 49
248 #define CLK_CPU_C0_CORE 2
295 #define CLK_ISP_BUS 49
[all …]
H A Dmediatek,mt8196-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
15 #define CLK_TOP_IO_NOC 2
62 #define CLK_TOP_MCUPM 49
147 #define CLK_APMIXED_MSDCPLL 2
157 #define CLK_TOP2_SENINF2 2
204 #define CLK_TOP2_MMPLL2_D4 49
229 #define CLK_APMIXED2_MMPLL2 2
241 #define CLK_IMPW_I2C6 2
247 #define CLK_IMPN_I2C4 2
255 #define CLK_IMPC_I2C13 2
[all …]
H A Dmt2701-clk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define CLK_TOP_SYSPLL_D2 2
59 #define CLK_TOP_TVDPLL_D4 49
176 #define CLK_APMIXED_MAINPLL 2
194 #define CLK_DDRPHY_NR 2
199 #define CLK_INFRA_SMI 2
223 #define CLK_PERI_THERM 2
272 #define CLK_PERI_NR 49
277 #define CLK_AUD_LRCK_DETECT 2
326 #define CLK_AUD_MMIF_DLMCH 49
[all …]
H A Dimx8ulp-clock.h1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
56 #define IMX8ULP_CLK_FROSC_DIV2_GATE 49
69 #define IMX8ULP_CLK_PLL4_VCODIV 2
117 #define IMX8ULP_CLK_CGC2_END 49
122 #define IMX8ULP_CLK_LPIT1 2
174 #define IMX8ULP_CLK_TPM7 2
201 #define IMX8ULP_CLK_SAI7 2
248 #define IMX8ULP_CLK_DMA2_CH29 49
H A Dmt7986-clk.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
14 #define CLK_APMIXED_MMPLL 2
25 #define CLK_TOP_RTC_32K 2
72 #define CLK_TOP_A1SYS_SEL 49
92 #define CLK_INFRA_UART1_SEL 2
139 #define CLK_INFRA_IUSB_SYS_CK 49
151 #define CLK_SGMII0_CDR_REF 2
158 #define CLK_SGMII1_CDR_REF 2
165 #define CLK_ETH_GP1_EN 2
H A Dpistachio-clk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define CLK_RPU_V_PLL 2
18 /* Fixed-factor clocks */
40 #define CLK_UART1 49
110 #define PERIPH_CLK_DDR 2
141 #define PERIPH_CLK_I2C2_DIV 49
150 #define SYS_CLK_I2C2 2
178 #define EXT_CLK_NR_CLKS 2
H A Dmt6779-clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define CLK_TOP_MM 2
59 #define CLK_TOP_MAINPLL_D2_D4 49
167 #define CLK_APMIXED_ARMPLL_BL 2
194 #define CLK_CAM_DFP_VAD 2
210 #define CLK_INFRA_PMIC_AP 2
257 #define CLK_INFRA_CCIF_MD 49
320 #define CLK_MFGCFG_NR_CLK 2
324 #define CLK_IMG_MFB 2
332 #define CLK_IPE_LARB8 2
[all …]
H A Daspeed,ast2700-scu.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
14 #define SCU0_CLK_192M 2
43 /* SOC0 clk-gate */
64 #define SCU0_CLK_GATE_CRT1CLK 49
78 #define SCU1_CLK_APLL 2
127 #define SCU1_CLK_GATE_UART3CLK 49
/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
18 .sample_patrn_length = 2,
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
31 { 0, -12, 113, 7, 32, -5, 0 },
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8183.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "pinctrl-mtk-mt8183.h"
10 #include "pinctrl-paris.h"
13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
50 PINS_FIELD_BASE(13, 16, 2, 0x000, 0x10, 2, 1),
51 PINS_FIELD_BASE(17, 20, 2, 0x000, 0x10, 3, 1),
52 PINS_FIELD_BASE(21, 24, 2, 0x000, 0x10, 4, 1),
53 PINS_FIELD_BASE(25, 28, 2, 0x000, 0x10, 5, 1),
54 PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 6, 1),
55 PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 7, 1),
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
33 RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
34 RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
37 RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
93 RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
111 RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
128 RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
[all …]
/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <media/v4l2-vp9.h>
46 { 55, 27, 12, 153, 203, 218, 26, 27, 49 }, /*left = d207*/
47 { 53, 49, 21, 110, 116, 168, 59, 80, 76 }, /*left = d63 */
72 { 64, 19, 37, 156, 66, 138, 49, 95, 133 }, /*left = dc */
80 { 45, 26, 28, 129, 45, 129, 49, 147, 123 }, /*left = d63 */
92 { 37, 49, 25, 129, 168, 164, 41, 54, 148 }, /*left = tm */
99 { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/
120 { 49, 50, 35, 144, 95, 205, 63, 78, 59 }, /*left = d135*/
131 /* 8x8 -> 4x4 */
[all …]
/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
12 # 2. c += d; b ^= c; b <<<= 12;
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
197 vadduwm 2, 2, 6
206 vpermxor 14, 14, 2, 25
243 vadduwm 2, 2, 6
254 vpermxor 14, 14, 2, 25
[all …]
/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
59 Sysreg OSDTRRX_EL1 2 0 0 0 2
64 Sysreg MDCCINT_EL1 2 0 0 2 0
71 Sysreg MDSCR_EL1 2 0 0 2 2
99 Sysreg OSDTRTX_EL1 2 0 0 3 2
104 Sysreg MDSELR_EL1 2 0 0 4 2
110 Sysreg MDSTEPOP_EL1 2 0 0 5 2
115 Sysreg OSECCR_EL1 2 0 0 6 2
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-pinfunc.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
12 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
19 * gpio nr: gpio number, 0 - 63
32 #define GPOUT_SYS_WAVE511_UART_TX 2
79 #define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49
140 #define GPOUT_AON_CLK_32K_OUT 2
152 #define GPOEN_SYS_HDMI_CEC_SDA 2
199 #define GPOEN_SYS_SPI6_NSSP 49
202 #define GPOEN_AON_PTC0_OE_N_4 2
212 #define GPI_SYS_USB_OVERCURRENT 2
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_gtf.c1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_main.h -- Intel 810 Non-discrete Video Timings
20 * FIFO and Watermark tables - based almost wholly on i810_wmark.c in
33 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
47 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
61 { 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
74 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
88 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
102 { 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
116 * i810fb_encode_registers - encode @var to hardware register values
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dsprd,spi-adi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
20 ADI controller has 50 channels including 2 software read/write channels and
21 48 hardware channels to access analog chip. For 2 software read/write channels,
[all …]
/linux/drivers/mfd/
H A Dqcom_rpm.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/mfd/qcom-rpm.h>
60 #define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
61 #define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
62 #define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
94 [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
95 [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
96 [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
97 [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
98 [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0-only
36 #define OTX2_CPT_LF_MSIX_VECTORS 2
153 * OcteonTX2 CPT VF MSI-X Vector Enumeration
154 * Enumerates the MSI-X interrupt vectors.
163 * OcteonTX2 CPT LF MSI-X Vector Enumeration
164 * Enumerates the MSI-X interrupt vectors.
176 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
188 * Address must be 16-byte aligned.
189 * Bits <63:49> are ignored by hardware; software should use a
190 * sign-extended bit <48> for forward compatibility.
[all …]

12345678910>>...45