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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,ethsys.yaml33 maxItems: 1
36 const: 1
39 const: 1
50 clock-controller@1b000000 {
53 #clock-cells = <1>;
54 #reset-cells = <1>;
H A Dmediatek,mt8192-clock.yaml41 maxItems: 1
44 const: 1
57 #clock-cells = <1>;
64 #clock-cells = <1>;
71 #clock-cells = <1>;
78 #clock-cells = <1>;
85 #clock-cells = <1>;
92 #clock-cells = <1>;
99 #clock-cells = <1>;
106 #clock-cells = <1>;
[all …]
H A Dmediatek,mt8195-clock.yaml53 maxItems: 1
56 const: 1
69 #clock-cells = <1>;
76 #clock-cells = <1>;
83 #clock-cells = <1>;
90 #clock-cells = <1>;
97 #clock-cells = <1>;
104 #clock-cells = <1>;
111 #clock-cells = <1>;
118 #clock-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Darm,hdlcd.yaml24 maxItems: 1
27 maxItems: 1
33 maxItems: 1
37 maxItems: 1
43 maxItems: 1
62 hdlcd@2b000000 {
77 #address-cells = <1>;
/linux/arch/powerpc/kernel/
H A Ddawr.c31 * doublewords (64 bits) biased by -1 eg. 0b000000=1DW and in set_dawr()
36 mrd = ((brk->hw_len + 7) >> 3) - 1; in set_dawr()
/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl9301-switch.yaml31 maxItems: 1
42 const: 1
45 const: 1
70 ethernet-switch@1b000000 {
76 #address-cells = <1>;
77 #size-cells = <1>;
88 #address-cells = <1>;
93 #address-cells = <1>;
105 #address-cells = <1>;
119 #address-cells = <1>;
[all …]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi6 #address-cells = <1>;
7 #size-cells = <1>;
17 #interrupt-cells = <1>;
22 #address-cells = <1>;
45 switch0: switch@1b000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
64 #address-cells = <1>;
72 #address-cells = <1>;
80 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts5 * CoreTile Express A15x2 (version with Test Chip 1)
35 #address-cells = <1>;
44 cpu@1 {
47 reg = <1>;
70 hdlcd@2b000000 {
103 interrupts = <1 9 0xf04>;
129 interrupts = <1 13 0xf08>,
130 <1 14 0xf08>,
131 <1 11 0xf08>,
132 <1 10 0xf08>;
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
70 maxItems: 1
121 #address-cells = <1>;
122 #size-cells = <1>;
128 #address-cells = <1>;
129 #size-cells = <1>;
163 icssg0: icssg@b000000 {
167 #address-cells = <1>;
168 #size-cells = <1>;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-conn.dtsi38 conn_subsys: bus@5b000000 {
40 #address-cells = <1>;
41 #size-cells = <1>;
60 #index-cells = <1>;
163 #address-cells = <1>;
164 #size-cells = <1>;
210 #clock-cells = <1>;
224 #clock-cells = <1>;
238 #clock-cells = <1>;
252 #clock-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi19 #address-cells = <1>;
20 #size-cells = <1>;
23 #address-cells = <1>;
35 cpu1: cpu@1 {
58 clk40m: oscillator-1 {
77 #address-cells = <1>;
78 #size-cells = <1>;
84 #clock-cells = <1>;
90 #clock-cells = <1>;
96 #power-domain-cells = <1>;
[all …]
H A Dmt2701.dtsi24 #address-cells = <1>;
33 cpu@1 {
80 rtc32k: oscillator@1 {
102 target: trip-point@1 {
129 #clock-cells = <1>;
135 #clock-cells = <1>;
136 #reset-cells = <1>;
142 #clock-cells = <1>;
143 #reset-cells = <1>;
153 #power-domain-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx.dtsi16 #address-cells = <1>;
17 #size-cells = <1>;
46 #address-cells = <1>;
92 /* OPP100-1 */
122 /* OPP120-1 */
136 /* OPP Turbo-1 */
157 target-module@4b000000 {
162 #address-cells = <1>;
163 #size-cells = <1>;
170 #address-cells = <1>;
[all …]
/linux/arch/arm64/tools/
H A Dsysreg95 Res0 5:1
120 Sysreg OSLAR_EL1 2 0 1 0 4
121 Res0 63:1
281 UnsignedEnum 1:0 P0
339 Sysreg SPMINTENSET_EL1 2 0 9 14 1
364 Field 1 P
368 Sysreg SPMCNTENSET_EL0 2 3 9 12 1
388 Field 1:0 BANK
400 Res0 3:1
404 Sysreg ID_PFR0_EL1 3 0 0 1 0
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi16 #address-cells = <1>;
17 #size-cells = <1>;
22 #address-cells = <1>;
58 #address-cells = <1>;
76 #address-cells = <1>;
94 #address-cells = <1>;
112 #address-cells = <1>;
206 img,voltage-select = <1>;
222 #address-cells = <1>;
232 dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi86 cpu1: cpu@1 {
217 #clock-cells = <1>;
218 #reset-cells = <1>;
237 #clock-cells = <1>;
238 #reset-cells = <1>;
244 #power-domain-cells = <1>;
278 #address-cells = <1>;
279 #size-cells = <1>;
293 #clock-cells = <1>;
299 #clock-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-main.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
40 #msi-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <1>;
53 #phy-cells = <1>;
59 #clock-cells = <1>;
99 #mbox-cells = <1>;
177 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
232 #mbox-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra264.dtsi57 nvidia,int-threshold = <1>;
58 #timestamp-cells = <1>;
97 #dma-cells = <1>;
99 iommu-map = <1 &smmu1 0x801 31>;
204 #dma-cells = <1>;
238 #address-cells = <1>;
249 i2s1_port: port@1 {
250 reg = <1>;
273 #address-cells = <1>;
284 i2s2_port: port@1 {
[all …]
/linux/arch/m68k/ifpsp060/
H A Dfplsp.sa16 dc.l $60ff0000,$1d160000,$60ff0000,$1da80000
17 dc.l $60ff0000,$1e3e0000,$60ff0000,$1ed60000
18 dc.l $60ff0000,$1f680000,$60ff0000,$1ffe0000
19 dc.l $60ff0000,$1b0e0000,$60ff0000,$1ba00000
20 dc.l $60ff0000,$1c360000,$60ff0000,$08860000
24 dc.l $60ff0000,$2a4c0000,$60ff0000,$2b000000
71 dc.l $ff6c41ee,$ff6c61ff,$00006c76,$1d40ff4e
101 dc.l $00006a9e,$1d40ff4e,$120002ae,$00ff00ff
130 dc.l $ff6c41ee,$ff6c61ff,$000068c6,$1d40ff4e
160 dc.l $000066ee,$1d40ff4e,$120002ae,$00ff00ff
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650.dtsi55 clock-mult = <1>;
64 clock-mult = <1>;
297 clocks = <&cpufreq_hw 1>;
307 qcom,freq-domain = <&cpufreq_hw 1>;
340 clocks = <&cpufreq_hw 1>;
350 qcom,freq-domain = <&cpufreq_hw 1>;
465 gold_cpu_sleep_0: cpu-sleep-1-0 {
495 cluster_sleep_1: cluster-sleep-1 {
519 ete-1 {
621 #address-cells = <1>;
[all …]