Home
last modified time | relevance | path

Searched +full:1 +full:v2 (Results 1 – 25 of 1209) sorted by relevance

12345678910>>...49

/freebsd/sys/crypto/openssl/aarch64/
H A Dvpsm4_ex-armv8.S74 cbnz w2,1f
76 1:
77 mov w7,v5.s[1]
87 ushr v2.16b, v0.16b, 4
90 tbl v2.16b, {v27.16b}, v2.16b
91 eor v0.16b, v0.16b, v2.16b
94 ushr v2.16b, v0.16b, 4
97 tbl v2.16b, {v29.16b}, v2.16b
98 eor v0.16b, v0.16b, v2.16b
112 subs x6,x6,#1
[all …]
H A Dvpsm4-armv8.S87 cbnz w2,1f
89 1:
90 mov w7,v5.s[1]
119 subs x6,x6,#1
120 b.ne 1b
140 movi v2.16b,#192
143 sub v2.16b,v12.16b,v2.16b
147 tbl v2.16b,{v28.16b,v29.16b,v30.16b,v31.16b},v2.16b
149 add v2.2d,v2.2d,v12.2d
150 add v12.2d,v0.2d,v2.2d
[all …]
H A Daes-gcm-armv8_64.S41 sub x5, x5, #1 //byte_len - 1
48 fmov d1, x10 //CTR block 1
51 add w12, w12, #1 //increment rev_ctr32
55 rev w9, w12 //CTR block 1
56 add w12, w12, #1 //CTR block 1
59 orr x9, x11, x9, lsl #32 //CTR block 1
62 fmov v1.d[1], x9 //CTR block 1
67 add w12, w12, #1 //CTR block 2
69 fmov v2.d[1], x9 //CTR block 2
75 add w12, w12, #1 //CTR block 3
[all …]
H A Dghashv8-armx.S17 dup v17.4s,v17.s[1]
22 shl v3.2d,v3.2d,#1
25 orr v3.16b,v3.16b,v18.16b //H<<<=1
31 pmull v0.1q,v20.1d,v20.1d
33 pmull2 v2.1q,v20.2d,v20.2d
34 pmull v1.1q,v16.1d,v16.1d
36 ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
37 eor v18.16b,v0.16b,v2.16b
40 pmull v18.1q,v0.1d,v19.1d //1st phase
42 ins v2.d[0],v1.d[1]
[all …]
H A Daes-gcm-armv8-unroll8_64.S26 mov v31.d[1], x15
30 sub x5, x5, #1 //byte_len - 1
32 …and x5, x5, #0xffffffffffffff80 //number of bytes to be processed in main loop (at least 1 byte m…
38 rev32 v1.16b, v30.16b //CTR block 1
39 add v30.4s, v30.4s, v31.4s //CTR block 1
41 rev32 v2.16b, v30.16b //CTR block 2
70 aesmc v1.16b, v1.16b //AES block 1 - round 0
71 aese v2.16b, v26.16b
72 aesmc v2.16b, v2.16b //AES block 2 - round 0
81 aesmc v3.16b, v3.16b //AES block 3 - round 1
[all …]
H A Dsm3-armv8.S32 ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x1], #64
33 sub w2, w2, #1
41 rev32 v2.16b, v2.16b
47 ext v4.16b, v1.16b, v2.16b, #12
51 ext v23.16b, v2.16b, v3.16b, #8
56 shl v21.4s, v20.4s, #1
61 shl v20.4s, v21.4s, #1
63 .inst 0xce5692e5 //sm3tt1a v5.4s, v23.4s, v22.4s[1]
64 .inst 0xce409ae6 //sm3tt2a v6.4s, v23.4s, v0.4s[1]
66 shl v21.4s, v20.4s, #1
[all …]
H A Dbsaes-armv8.S54 sub x10, x10, #1
57 eor v2.16b, v2.16b, v8.16b
63 tbl v2.16b, {v2.16b}, v10.16b
70 ushr v8.2d, v0.2d, #1
72 ushr v10.2d, v4.2d, #1
73 ushr v18.2d, v2.2d, #1
75 ushr v19.2d, v6.2d, #1
83 shl v8.2d, v8.2d, #1
86 shl v10.2d, v10.2d, #1
88 shl v18.2d, v18.2d, #1
[all …]
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-riscv64-zvkb-zvbc.pl19 # 1. Redistributions of source code must retain the above copyright
69 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
86 @{[vle64_v $V2, $TMP2]} # vle64.v v2, (t2)
90 @{[vsll_vi $V1, $V1, 1]} # vsll.vi v1, v1, 1
97 @{[vslideup_vi $V4, $V3, 1]} # vslideup.vi v4, v3, 1
98 @{[vslidedown_vi $V3, $V3, 1]} # vslidedown.vi v3, v3, 1
109 @{[vxor_vv_v0t $V1, $V1, $V2]} # vxor.vv v1, v1, v2, v0.t
125 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
167 # v2 = (a1b1)h,(a1b0)h
168 @{[vclmulh_vx $V2, $V5, $TMP1]} # vclmulh.vx v2, v5, t1
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/advsimd/
H A Derfinv_25u.c30 { 0x1.74e5f6ceb3548p+7, -0x1.779bb9bef7c0fp+1 },
38 { 0x1.a450d8e7f4cbbp+7, -0x1.3413109467a0bp+1 },
43 .P_57 = { V2 (0x1.b874f9516f7f1p-14), V2 (0x1.5921f2916c1c4p-7),
44 V2 (0x1.145ae7d5b8fa4p-2), V2 (0x1.29d6dcc3b2fb7p+1),
45 V2 (0x1.cabe2209a7985p+2), V2 (0x1.11859f0745c4p+3),
46 V2 (0x1.b7ec7bc6a2ce5p+2), V2 (0x1.d0419e0bb42aep+1),
47 V2 (0x1.c5aa03eef7258p-1) },
48 .Q_57 = { V2 (0x1.b8747e12691f1p-14), V2 (0x1.59240d8ed1e0ap-7),
49 V2 (0x1.14aef2b181e2p-2), V2 (0x1.2cd181bcea52p+1),
50 V2 (0x1.e6e63e0b7aa4cp+2), V2 (0x1.65cf8da94aa3ap+3),
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/advsimd/
H A Dv_sincos_common.h16 .inv_pio2 = V2 (0x1.45f306dc9c882p-1),
17 .pio2 = { V2 (0x1.921fb50000000p+0), V2 (0x1.110b460000000p-26),
18 V2 (0x1.1a62633145c07p-54) },
19 .shift = V2 (0x1.8p52),
21 V2 (-0x1.555555555547bp-3), V2 (0x1.1111111108a4dp-7),
22 V2 (-0x1.a01a019936f27p-13), V2 (0x1.71de37a97d93ep-19),
23 V2 (-0x1.ae633919987c6p-26), V2 (0x1.60e277ae07cecp-33),
24 V2 (-0x1.9e9540300a1p-41) },
26 V2 (0x1.555555555554cp-5), V2 (-0x1.6c16c16c1521fp-10),
27 V2 (0x1.a01a019cbf62ap-16), V2 (-0x1.27e4f812b681ep-22),
[all …]
H A Dv_sincospi_common.h16 .poly = { V2 (0x1.921fb54442d184p1), V2 (-0x1.4abbce625be53p2),
17 V2 (0x1.466bc6775ab16p1), V2 (-0x1.32d2cce62dc33p-1),
18 V2 (0x1.507834891188ep-4), V2 (-0x1.e30750a28c88ep-8),
19 V2 (0x1.e8f48308acda4p-12), V2 (-0x1.6fc0032b3c29fp-16),
20 V2 (0x1.af86ae521260bp-21), V2 (-0x1.012a9870eeb7dp-25) },
21 .range_val = V2 (0x1p63),
29 _ZGVnN2v_sincospi_sin(0x1.7a41deb4b21e1p+14) got 0x1.fd54d0b327cf1p-1
30 want 0x1.fd54d0b327cf4p-1
32 _ZGVnN2v_sincospi_cos(-0x1.11e3c7e284adep-5) got 0x1.fd2da484ff3ffp-1
33 want 0x1.fd2da484ff402p-1. */
[all …]
H A Dacos.c21 .poly = { V2 (0x1.555555555554ep-3), V2 (0x1.3333333337233p-4),
22 V2 (0x1.6db6db67f6d9fp-5), V2 (0x1.f1c71fbd29fbbp-6),
23 V2 (0x1.6e8b264d467d6p-6), V2 (0x1.1c5997c357e9dp-6),
24 V2 (0x1.c86a22cd9389dp-7), V2 (0x1.856073c22ebbep-7),
25 V2 (0x1.fd1151acb6bedp-8), V2 (0x1.087182f799c1dp-6),
26 V2 (-0x1.6602748120927p-7), V2 (0x1.cfa0dd1f9478p-6), },
27 .pi = V2 (0x1.921fb54442d18p+1),
28 .pi_over_2 = V2 (0x1.921fb54442d18p+0),
29 .abs_mask = V2 (0x7fffffffffffffff),
62 acos(x) = y + y * z * P(z), with z = (1-x)/2 and y = sqrt(z).
[all …]
H A Dasinh.c27 .tiny_bound = V2 (0x1p-26),
33 .c0 = V2 (-0x1.55555555554a7p-3),
35 .c2 = V2 (-0x1.6db6db68332e6p-5),
37 .c4 = V2 (-0x1.6e8b8b654a621p-6),
38 .c5 = 0x1.1c4daa9e67871p-6,
39 .c6 = V2 (-0x1.c9871d10885afp-7),
41 .c8 = V2 (-0x1.3ddca533e9f54p-7),
43 .c10 = V2 (-0x1.b90c7099dd397p-8),
45 .c12 = V2 (-0x1.d217026a669ecp-9),
47 .c14 = V2 (-0x1.e0f37daef9127p-11),
[all …]
H A Dv_log_inline.h18 V2 (-0x1.ffffffffcbad3p-2), V2 (0x1.555555578ed68p-2), \
19 V2 (-0x1.0000d3a1e7055p-2), V2 (0x1.999392d02a63ep-3) \
24 V2 (-0x1.ffffffffffff7p-2), V2 (0x1.55555555170d4p-2), \
25 V2 (-0x1.0000000399c27p-2), V2 (0x1.999b2e90e94cap-3), \
26 V2 (-0x1.554e550bd501ep-3) \
41 .poly = POLY, .ln2 = V2 (0x1.62e42fefa39efp-1), \
42 .sign_exp_mask = V2 (0xfff0000000000000), .off = V2 (0x3fe6900900000000) \
46 #define N (1 << V_LOG_TABLE_BITS)
47 #define IndexMask (N - 1)
58 /* Since N is a power of 2, n % N = n & (N - 1). */ in log_lookup()
[all …]
H A Dcospi.c21 .poly = { V2 (0x1.921fb54442d184p1), V2 (-0x1.4abbce625be53p2),
22 V2 (0x1.466bc6775ab16p1), V2 (-0x1.32d2cce62dc33p-1),
23 V2 (0x1.507834891188ep-4), V2 (-0x1.e30750a28c88ep-8),
24 V2 (0x1.e8f48308acda4p-12), V2 (-0x1.6fc0032b3c29fp-16),
25 V2 (0x1.af86ae521260bp-21), V2 (-0x1.012a9870eeb7dp-25) },
26 .range_val = V2 (0x1p63),
39 _ZGVnN2v_cospi(0x1.7dd4c0b03cc66p-5) got 0x1.fa854babfb6bep-1
40 want 0x1.fa854babfb6c1p-1. */
49 /* When WANT_SIMD_EXCEPT = 1, special lanes should be zero'd in V_NAME_D1()
64 /* cospi(x) = sinpi(0.5 - abs(x)) for values -1/2 .. 1/2. */ in V_NAME_D1()
/freebsd/crypto/krb5/src/util/support/
H A Dt_json.c14 * 1. Redistributions of source code must retain the above copyright
78 exit(1); in err()
92 k5_json_number v2; in test_array() local
100 k5_json_number_create(2, &v2); in test_array()
101 k5_json_array_add(a, v2); in test_array()
108 v = k5_json_array_get(a, 1); in test_array()
109 check(k5_json_get_tid(v) == K5_JSON_TID_NUMBER, "array[1] tid"); in test_array()
110 check(k5_json_number_value(v) == 2, "array[1] value"); in test_array()
116 k5_json_release(v2); in test_array()
119 k5_json_array_fmt(&a, "vnbiLssB", v3, 1, 9, (long long)-6, "def", NULL, in test_array()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2.yaml4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
39 operating-points-v2 = <&cpu0_opp_table0>;
42 cpu@1 {
45 reg = <1>;
50 operating-points-v2 = <&cpu0_opp_table0>;
55 compatible = "operating-points-v2";
[all …]
H A Dopp.txt13 Binding 1: operating-points
39 Binding 2: operating-points-v2
42 * Property: operating-points-v2
44 Devices supporting OPPs must set their "operating-points-v2" property with
55 and should have a compatible description like: "operating-points-v2-<vendor>".
64 "operating-points-v2".
191 Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
195 #address-cells = <1>;
205 operating-points-v2 = <&cpu0_opp_table>;
208 cpu@1 {
[all …]
/freebsd/contrib/bsnmp/lib/
H A Dsnmp.h18 * 1. Redistributions of source code must retain the above copyright
45 #define BSNMP_MAJOR 1
50 #define SNMP_CONTEXT_NAME_SIZ (32 + 1)
64 /* v2 additions */
90 SNMP_V1 = 1,
96 #define SNMP_MPM_SNMP_V2c 1
99 #define SNMP_ADM_STR32_SIZ (32 + 1)
112 SNMP_SECMODEL_SNMPv1 = 1,
119 SNMP_noAuthNoPriv = 1,
132 SNMP_PRIV_DES = 1,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,saw2.yaml31 - qcom,sdm660-gold-saw2-v4.1-l2
32 - qcom,sdm660-silver-saw2-v4.1-l2
33 - qcom,msm8998-gold-saw2-v4.1-l2
34 - qcom,msm8998-silver-saw2-v4.1-l2
38 - qcom,msm8226-saw2-v2.1-cpu
39 - qcom,msm8226-saw2-v2.1-l2
41 - qcom,msm8974-saw2-v2.1-cpu
42 - qcom,msm8974-saw2-v2.1-l2
43 - qcom,msm8976-gold-saw2-v2.3-l2
44 - qcom,msm8976-silver-saw2-v2.3-l2
[all …]
H A Dqcom,spm.yaml21 - qcom,sdm660-gold-saw2-v4.1-l2
22 - qcom,sdm660-silver-saw2-v4.1-l2
23 - qcom,msm8998-gold-saw2-v4.1-l2
24 - qcom,msm8998-silver-saw2-v4.1-l2
28 - qcom,msm8226-saw2-v2.1-cpu
29 - qcom,msm8974-saw2-v2.1-cpu
30 - qcom,msm8976-gold-saw2-v2.3-l2
31 - qcom,msm8976-silver-saw2-v2.3-l2
32 - qcom,apq8084-saw2-v2.1-cpu
33 - qcom,apq8064-saw2-v1.1-cpu
[all …]
/freebsd/secure/usr.bin/openssl/man/
H A Dopenssl-pkcs8.146 . tm Index:\\$1\t\\n%\t"\\$2"
57 .IX Title "OPENSSL-PKCS8 1ossl"
58 .TH OPENSSL-PKCS8 1ossl 2025-09-30 3.5.4 OpenSSL
80 [\fB\-v2\fR \fIalg\fR]
99 format with a variety of PKCS#5 (v1.5 and v2.0) and PKCS#12 algorithms.
113 See \fBopenssl\-format\-options\fR\|(1) for details.
143 see \fBopenssl\-passphrase\-options\fR\|(1).
161 When creating new PKCS#8 containers, use 1 as iteration count.
170 .IP "\fB\-v2\fR \fIalg\fR" 4
171 .IX Item "-v2 alg"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Darm,smmu.yaml15 Management Unit Architecture, which can be used to provide 1 or 2 stages
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
119 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2
[all …]
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha256-riscv64-zvkb-zvknha_or_zvknhb.pl20 # 1. Redistributions of source code must retain the above copyright
63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
134 @{[vsetivli "zero", 1, "e32", "m1", "ta", "ma"]}
146 @{[vsetivli "zero", 1, "e8", "m1", "ta", "ma"]}
152 # Decrement length by 1
153 add $LEN, $LEN, -1
164 @{[vle32_v $V2, $INP]}
165 @{[vrev8_v $V2, $V2]}
174 # Quad-round 0 (+0, Wt from oldest to newest in v1->v2->v3->v4)
178 @{[vmerge_vvm $V5, $V3, $V2, $V0]}
[all …]
/freebsd/crypto/openssl/crypto/aes/asm/
H A Dbsaes-armv8.pl15 $0 =~ m/(.*[\/\\])[^\/\\]+$/; my $dir=$1;
87 sub x10, x10, #1
90 eor v2.16b, v2.16b, v8.16b
96 tbl v2.16b, {v2.16b}, v10.16b
103 ushr v8.2d, v0.2d, #1
105 ushr v10.2d, v4.2d, #1
106 ushr v18.2d, v2.2d, #1
108 ushr v19.2d, v6.2d, #1
116 shl v8.2d, v8.2d, #1
119 shl v10.2d, v10.2d, #1
[all …]

12345678910>>...49