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/linux/include/linux/ssb/
H A Dssb_regs.h16 #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
20 #define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
21 #define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */
23 #define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
44 #define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */
47 #define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */
64 #define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */
98 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
185 /* SPROM Revision 1 */
196 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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H A Dssb.h48 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
49 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
63 u8 gpio1; /* GPIO pin 1 */
66 u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
67 u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
68 u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
69 u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
72 u8 tri2g; /* 2.4GHz TX isolation */
73 u8 tri5gl; /* 5.2GHz TX isolation */
74 u8 tri5g; /* 5.3GHz TX isolation */
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admfm2000.yaml15 from 0.5 to 32 GHz and an output IF frequency range from 0.1 to 8 GHz.
25 const: 1
31 "^channel@[0-1]$":
42 maximum: 1
46 Enable mixer mode for the channel. It downconverts RF between 5 GHz
47 and 32 GHz to IF between 0.5 GHz and 8 GHz. If not present, the channel
49 between 2 GHz and 8 GHz to IF between 0.5 GHz and 8 GHz.
57 1 0 Direct IF mode Mixer mode
58 0 1 Mixer mode Direct IF mode
68 1 1 1 1 1 0 dB
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-netgear-r8500.dts39 led-5ghz-1 {
40 label = "bcm53xx:white:5ghz-1";
44 led-5ghz-2 {
45 label = "bcm53xx:white:5ghz-2";
49 led-2ghz {
50 label = "bcm53xx:white:2ghz";
71 gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
H A Dbcm47189-luxul-xap-810.dts26 led-5ghz {
27 label = "bcm53xx:blue:5ghz";
38 leds-1 {
41 led-2ghz {
42 label = "bcm53xx:blue:2ghz";
69 wifi@0,1,0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
92 /delete-node/ switch@1e;
H A Dbcm947189acdbmr.dts33 led-5ghz {
34 label = "bcm53xx:blue:5ghz";
38 led-2ghz {
39 label = "bcm53xx:blue:2ghz";
62 num-chipselects = <1>;
67 #address-cells = <1>;
85 wifi@0,1,0 {
88 #address-cells = <1>;
89 #size-cells = <1>;
H A Dbcm47189-tenda-ac9.dts28 gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
38 led-5ghz {
39 label = "bcm53xx:blue:5ghz";
50 leds-1 {
53 led-2ghz {
54 label = "bcm53xx:blue:2ghz";
93 wifi@0,1,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
117 port@1 {
H A Dbcm47081-luxul-xap-1410.dts23 nvram@1eff0000 {
34 led-5ghz {
35 label = "bcm53xx:blue:5ghz";
40 led-2ghz {
41 label = "bcm53xx:blue:2ghz";
H A Dbcm4708-luxul-xap-1510.dts23 nvram@1eff0000 {
34 led-5ghz {
35 label = "bcm53xx:blue:5ghz";
40 led-2ghz {
41 label = "bcm53xx:blue:2ghz";
H A Dbcm47094-luxul-xwr-3100.dts25 nvram@1eff0000 {
30 #nvmem-cell-cells = <1>;
45 gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
82 led-2ghz {
83 label = "bcm53xx:green:2ghz";
87 led-5ghz {
88 label = "bcm53xx:green:5ghz";
129 port@1 {
H A Dbcm47081-luxul-xwr-1200.dts24 nvram@1eff0000 {
29 #nvmem-cell-cells = <1>;
44 gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
79 led-2ghz {
80 label = "bcm53xx:green:2ghz";
85 led-5ghz {
86 label = "bcm53xx:green:5ghz";
130 port@1 {
H A Dbcm47094-dlink-dir-885l.dts28 nvram@1e3f0000 {
33 #nvmem-cell-cells = <1>;
41 #address-cells = <1>;
42 #size-cells = <1>;
64 gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
85 led-2ghz {
86 label = "bcm53xx:white:2ghz";
90 led-5ghz {
91 label = "bcm53xx:white:5ghz";
145 port@1 {
H A Dbcm47081-tplink-archer-c5-v2.dts26 led-2ghz {
27 label = "bcm53xx:green:2ghz";
33 gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
64 led-5ghz {
65 label = "bcm53xx:green:5ghz";
H A Dbcm4709-tplink-archer-c9-v1.dts28 gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
36 led-2ghz {
37 label = "bcm53xx:blue:2ghz";
41 led-5ghz {
42 label = "bcm53xx:blue:5ghz";
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dscan.h62 #define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
63 #define CAN_ABORT_STATUS 1
73 SCAN_CLIENT_NETDETECT = BIT(1),
90 IWL_NETWORK_TYPE_BSS = 1,
184 IWL_SCAN_OFFLOAD_COMPLETED = 1,
217 * @flags: bits 1-20: directed scan to i'th ssid
219 * @channel_num: channel number 1-13 etc
270 IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE = BIT(1),
283 * 1 - EBS is disabled.
303 * 1, 6 and 11.
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/linux/arch/arm64/kernel/
H A Dwatchdog_hld.c9 * maximum frequency but 5 GHz seems to be safe maximum given the available
10 * Arm CPUs in the market which are clocked much less than 5 GHz. On the other
12 * detection timeout on parts which are running slower (eg. 1GHz on
15 #define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz
67 * (core 0/1 share the same policy) in watchdog_freq_notifier_callback()
68 * [core 0] [core 1] in watchdog_freq_notifier_callback()
74 * (since core 1's event's not yet created, in watchdog_freq_notifier_callback()
/linux/drivers/iio/amplifiers/
H A Dad8366.c8 * ADRF5702: 0.125 dB LSB, 8-Bit, Silicon Digital Attenuator, 50 MHz to 20 GHz
9 * ADRF5703: 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator, 9 kHz to 20 GHz
10 * ADRF5720: 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz
11 * ADRF5730: 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz
12 * ADRF5731: 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz
13 * HMC271A: 1dB LSB 5-Bit Digital Attenuator SMT, 0.7 - 3.7 GHz
15 * HMC1018A: 1.0 dB LSB GaAs MMIC 5-BIT DIGITAL ATTENUATOR, 0.1 - 30 GHz
16 * HMC1019A: 0.5 dB LSB GaAs MMIC 5-BIT DIGITAL ATTENUATOR, 0.1 - 30 GHz
66 u8 ch_b = bitrev8(code[1]) >> 2; in ad8366_pack_code()
76 return 1; in adrf5731_pack_code()
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/linux/drivers/net/wireless/intel/iwlwifi/mld/
H A Dscan.c35 /* adaptive dwell default APs number for P2P social channels (1, 6, 11) */
50 /* minimal number of 2GHz and 5GHz channels in the regular scan request */
198 ieee80211_vif_is_mld(curr_vif) ? curr_vif->active_links : 1; in iwl_mld_scan_iterator()
276 *newpos++ = 1; in iwl_mld_scan_add_2ghz_elems()
289 pos[1] = WFA_TPC_IE_LEN - 2; in iwl_mld_scan_add_tpc_report_elem()
314 return params->n_scan_plans == 1 && in iwl_mld_scan_is_regular()
315 params->scan_plans[0].iterations == 1; in iwl_mld_scan_is_regular()
355 return -1; in iwl_mld_scan_ssid_exist()
361 return -1; in iwl_mld_scan_ssid_exist()
403 /* Insert DS parameter set element on 2.4 GHz band */ in iwl_mld_scan_build_probe_req()
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/linux/drivers/net/wireless/ti/wlcore/
H A Dscan.h31 #define WL1271_SCAN_DEFAULT_TAG 1
34 #define WL1271_SCAN_OPT_PASSIVE 1
40 #define WL1271_SCAN_BAND_5_GHZ 1
65 * and 18xx (which have different max 5ghz channels value).
67 * max possible 5ghz channels.
74 * The 1st entry isn't used (scan is immediate). The last
82 SCAN_SSID_FILTER_SPECIFIC = 1,
95 #define SCAN_CHANNEL_FLAGS_DFS_ENABLED BIT(1)
105 /* bit 0: DFS channel; bit 1: DFS enabled */
115 SCAN_SSID_TYPE_HIDDEN = 1,
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/linux/drivers/net/wireless/ath/ath5k/
H A Deeprom.h34 #define AR5K_EEPROM_RFKILL_POLARITY_S 1
51 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */
53 #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2GHz (ar5211_rfregs) */
71 #define AR5K_EEPROM_MODE_11B 1
78 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2GHz */
80 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI…
82 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5GHz */
114 #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) /* modes supported by radio 0 (bit 1: G, bit 2…
115 #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) /* modes supported by radio 1 (bit 1: G, bit 2: A) */
119 #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) /* disable AES */
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/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.h85 * @scd_retry: (1) Indicates queue will be used in aggregation mode
264 * 1) EEPROM
270 * 1) Regulatory information (max txpower and channel usage flags) is provided
279 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
280 * but 5 GHz has several sub-bands.
282 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
291 * 1) Temperature calculation parameters.
299 * 1) Current values for temperature param R4.
307 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
320 * Backoff values below are in 1/2 dB units (equivalent to steps in
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-cm-fx6.dts182 fsl,audmux-port = <1>;
196 IMX_AUDMUX_V2_PTCR_TFSEL(1) |
198 IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) |
200 IMX_AUDMUX_V2_PTCR_TCSEL(1))
201 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
208 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
210 * 1.2GHz operation point here.
230 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
232 * 1.2GHz operation point here.
252 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
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/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4906-tplink-archer-c2300-v1.dts27 led-2ghz {
28 function = "2ghz";
33 led-5ghz {
34 function = "5ghz";
117 brcm,ioc = <1>;
138 port@1 {
168 #address-cells = <1>;
173 #address-cells = <1>;
174 #size-cells = <1>;
/linux/net/wireless/
H A Dutil.c54 return 1; in ieee80211_mandatory_rates()
72 * there are overlapping channel numbers in 5GHz and 2GHz bands */ in ieee80211_channel_to_freq_khz()
90 /* see 802.11ax D6.1 27.3.23.2 */ in ieee80211_channel_to_freq_khz()
126 /* see 802.11ax D6.1 27.3.22.2 */ in ieee80211_freq_khz_to_channel()
209 /* check for mandatory HT MCS 1..4 */ in set_mandatory_flags_band()
221 WARN_ON(1); in set_mandatory_flags_band()
311 * Extended Key ID - 1 as index for pairwise keys. in cfg80211_validate_key_settings()
322 if (pairwise && (key_idx < 0 || key_idx > 1)) in cfg80211_validate_key_settings()
585 return -1; in ieee80211_data_to_8023_exthdr()
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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