| /linux/lib/zstd/compress/ |
| H A D | clevels.h | 26 { 19, 12, 13, 1, 6, 1, ZSTD_fast }, /* base for negative levels */
27 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
31 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
32 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6 */
33 { 21, 19, 20, 4, 5, 8, ZSTD_lazy }, /* level 7 */
34 { 21, 19, 20, 4, 5, 16, ZSTD_lazy2 }, /* level 8 */
45 { 23, 24, 22, 7, 3,256, ZSTD_btultra2}, /* level 19 */
58 { 18, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6.*/
59 { 18, 18, 19, 4, 4, 4, ZSTD_lazy }, /* level 7 */
60 { 18, 18, 19, 4, 4, 8, ZSTD_lazy2 }, /* level 8 */
[all …]
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| /linux/arch/alpha/include/asm/ |
| H A D | xor.h | 65 ldq $19,32($17) \n\
83 xor $19,$20,$19 \n\
87 stq $19,32($17) \n\
112 ldq $2,0($19) \n\
123 ldq $5,8($19) \n\
125 ldq $20,16($19) \n\
126 ldq $23,24($19) \n\
127 ldq $27,32($19) \n\
157 ldq $2,40($19) \n\
158 ldq $5,48($19) \n\
[all …]
|
| /linux/drivers/gpu/drm/display/ |
| H A D | drm_dsc_helper.c | 166 /* PPS 18, 19 */ in drm_dsc_pps_payload_pack()
387 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
393 { 512, 12, 6144, 11, 20, 19, 19, {
396 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
418 { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
424 { 410, 12, 5632, 11, 20, 19, 19, {
428 { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
449 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
455 { 341, 15, 2048, 11, 20, 19, 19, {
458 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
[all …]
|
| /linux/include/dt-bindings/memory/ |
| H A D | mt8195-memory-port.h | 29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
119 #define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)
141 #define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)
236 #define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)
237 #define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1)
238 #define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2)
239 #define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3)
240 #define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4)
241 #define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)
242 #define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6)
[all …]
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| /linux/arch/arm64/crypto/ |
| H A D | sha512-ce-core.S | 15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
144 dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17
146 dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19
147 dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12
151 dround 3, 0, 4, 2, 1, 26, 30, 18, 19, 17, 14, 15
152 dround 2, 3, 1, 4, 0, 27, 31, 19, 12, 18, 15, 16
153 dround 4, 2, 0, 1, 3, 28, 24, 12, 13, 19, 16, 17
156 dround 0, 1, 2, 3, 4, 30, 26, 14, 15, 13, 18, 19
157 dround 3, 0, 4, 2, 1, 31, 27, 15, 16, 14, 19, 12
160 dround 1, 4, 3, 0, 2, 26, 30, 18, 19, 17, 14, 15
[all …]
|
| H A D | sha2-ce-core.S | 106 add_update 0, v1, 16, 17, 18, 19
107 add_update 1, v2, 17, 18, 19, 16
108 add_update 0, v3, 18, 19, 16, 17
109 add_update 1, v4, 19, 16, 17, 18
111 add_update 0, v5, 16, 17, 18, 19
112 add_update 1, v6, 17, 18, 19, 16
113 add_update 0, v7, 18, 19, 16, 17
114 add_update 1, v8, 19, 16, 17, 18
116 add_update 0, v9, 16, 17, 18, 19
117 add_update 1, v10, 17, 18, 19, 16
[all …]
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| /linux/arch/powerpc/crypto/ |
| H A D | chacha-p10le-8x.S | 88 SAVE_GPR 19, 152, 1
121 SAVE_VSX 19, 272, 9
156 RESTORE_VSX 19, 272, 9
175 RESTORE_GPR 19, 152, 1
205 vadduwm 19, 19, 23
214 vpermxor 31, 31, 19, 25
251 vadduwm 19, 19, 23
262 vpermxor 31, 31, 19, 25
302 vadduwm 19, 19, 20
311 vpermxor 30, 30, 19, 25
[all …]
|
| /linux/Documentation/translations/zh_CN/scheduler/ |
| H A D | sched-nice-design.rst | 16 Linux的nice级别总是非常脆弱，人们持续不断地缠着我们，让nice +19的任务占用
24 （人们对这一变化很满意），而且我们还故意校正了线性时间片准则，使得nice +19
40 -20 | +19
44 因此，如果有人真的想renice任务，相较线性规则，+19会给出更大的效果（改变
51 nice +19级别运行数量颇多的应用程序）。
53 因此，对于HZ=1000，我们将nice +19改为5毫秒，因为这感觉像是正确的最小
54 粒度——这相当于5%的CPU利用率。但nice +19的根本的HZ敏感属性依然保持不变，
55 我们没有收到过关于nice +19在CPU利用率方面太 _弱_ 的任何抱怨，我们只收到
87 更一致的nice +19支持：在新的调度器中，nice +19的任务得到一个HZ无关的
|
| /linux/arch/alpha/lib/ |
| H A D | csum_ipv6_magic.S | 64 extwh $19,7,$7 # e0 :
66 extbl $19,1,$19 # e0 :
69 or $19,$7,$19 # e0 :
71 sll $19,48,$19 # e0 :
74 sra $19,32,$19 # e0 : proto complete
82 addq $20,$19,$20 # .. e1 :
84 cmpult $20,$19,$19 # e0 :
87 addq $18,$19,$18 # .. e1 :
|
| H A D | ev6-csum_ipv6_magic.S | 67 sll $19,8,$7 # U : U L U L : 0x00000000 00aabb00
77 sll $19,24,$19 # U : U U L U : 0x000000aa bb000000
82 addl $19,$7,$19 # E : U L U L : <sign bits>bbaabb00
101 zap $19,0x3,$19 # U : <sign bits>bbaa0000
120 addq $20,$19,$20 # E : (1 cycle stall on $20)
124 cmpult $20,$19,$19 # E :
125 addq $18,$19,$18 # E : (1 cycle stall on $19)
|
| /linux/Documentation/admin-guide/acpi/ |
| H A D | cppc_sysfs.rst | 30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
35 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq
36 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_perf
37 -r--r--r-- 1 root root 65536 Mar 5 19:38 reference_perf
38 -r--r--r-- 1 root root 65536 Mar 5 19:38 wraparound_time
|
| /linux/arch/arm/mach-rpc/ |
| H A D | irq.c | 37 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
38 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
39 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
40 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
41 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
42 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
43 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
44 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
45 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
46 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
[all …]
|
| /linux/Documentation/scheduler/ |
| H A D | sched-nice-design.rst | 9 pestered us to make nice +19 tasks use up much less CPU time.
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
35 -20 | +19
39 So that if someone wanted to really renice tasks, +19 would give a much
49 people were running number crunching apps at nice +19.)
51 So for HZ=1000 we changed nice +19 to 5msecs, because that felt like the
53 But the fundamental HZ-sensitive property for nice+19 still remained,
54 and we never got a single complaint about nice +19 being too _weak_ in
93 it was possible to implement better and more consistent nice +19
94 support: with the new scheduler nice +19 tasks get a HZ-independent
|
| /linux/lib/zlib_inflate/ |
| H A D | inffixed.h | 13 {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},
16 {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},
20 {0,9,248},{16,7,3},{0,8,82},{0,8,18},{21,8,163},{19,7,35},{0,8,114},
23 {20,7,67},{0,8,122},{0,8,58},{0,9,212},{18,7,19},{0,8,106},{0,8,42},
25 {0,8,22},{64,8,0},{19,7,51},{0,8,118},{0,8,54},{0,9,204},{17,7,15},
32 {0,9,146},{19,7,59},{0,8,121},{0,8,57},{0,9,210},{17,7,17},{0,8,105},
34 {0,8,85},{0,8,21},{16,8,258},{19,7,43},{0,8,117},{0,8,53},{0,9,202},
38 {0,8,141},{0,8,77},{0,9,250},{16,7,3},{0,8,83},{0,8,19},{21,8,195},
39 {19,7,35},{0,8,115},{0,8,51},{0,9,198},{17,7,11},{0,8,99},{0,8,35},
41 {0,8,27},{0,9,150},{20,7,67},{0,8,123},{0,8,59},{0,9,214},{18,7,19},
[all …]
|
| /linux/Documentation/translations/zh_CN/core-api/ |
| H A D | packing.rst | 63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
122 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
132 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
143 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
|
| /linux/arch/alpha/kernel/ |
| H A D | entry.S | 72 stq $19, 72($sp)
90 .cfi_rel_offset $19, 72
102 lda $19, alpha_mv
108 ldq $20, HAE_CACHE($19)
116 ldq $20, HAE_REG($19)
117 stq $21, HAE_CACHE($19)
119 99: ldq $19, 72($sp)
139 .cfi_restore $19
185 mov $sp, $19
217 addq $sp, 56, $19
[all …]
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| /linux/drivers/video/logo/ |
| H A D | logo_spe_clut224.ppm | 7 15 15 15 21 21 21 19 19 19 14 14 14 6 6 6 2 2 2
20 0 0 0 0 0 0 2 2 2 27 27 27 62 62 62 17 17 19
91 240 192 13 240 192 13 240 192 13 215 161 11 207 152 19 81 64 9
127 244 244 244 19 19 21 2 2 6 2 2 6 2 2 6 38 38 38
145 0 0 0 0 0 0 0 0 0 6 6 6 59 59 59 19 19 21
152 0 0 0 0 0 0 0 0 0 16 16 16 67 67 67 19 19 21
173 0 0 0 4 4 4 39 39 39 42 42 43 19 19 21 13 13 13
176 228 210 210 253 253 253 253 253 253 122 122 122 2 2 6 19 19 19
194 5 5 5 22 22 22 104 96 81 187 136 12 207 152 19 51 48 39
214 0 0 0 0 0 0 0 0 0 4 4 4 53 53 53 207 152 19
[all …]
|
| /linux/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 832 { 0x3, 19, NULL, NULL, 0 },
1300 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) in insert_bo()
1330 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) in insert_boe()
1437 && (insn & (0x3ff << 1)) == 19 << 1))) in insert_fxm()
1441 else if ((insn & (0x3ff << 1)) == 19 << 1) in insert_fxm()
1469 else if ((insn & (0x3ff << 1)) == 19 << 1) in extract_fxm()
2543 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2612 #define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
4147 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4149 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
[all …]
|
| /linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu981_regs.h | 44 #define av1_pic_width_in_cbs AV1_DEC_REG(4, 19, 0x1fff)
65 #define av1_disable_cdf_update AV1_DEC_REG(5, 19, 0x1)
121 #define av1_multicore_tile_col AV1_DEC_REG(11, 19, 0x7f)
129 #define av1_multicore_tile_width AV1_DEC_REG(12, 19, 0x7f)
147 #define av1_filt_level_delta0_seg0 AV1_DEC_REG(14, 19, 0x7f)
154 #define av1_filt_level_delta0_seg1 AV1_DEC_REG(15, 19, 0x7f)
161 #define av1_filt_level_delta0_seg2 AV1_DEC_REG(16, 19, 0x7f)
168 #define av1_filt_level_delta0_seg3 AV1_DEC_REG(17, 19, 0x7f)
175 #define av1_filt_level_delta0_seg4 AV1_DEC_REG(18, 19, 0x7f)
178 #define av1_quant_seg5 AV1_DEC_REG(19, 0, 0xff)
[all …]
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| /linux/Documentation/admin-guide/media/ |
| H A D | ivtv.rst | 82 crw-rw---- 1 root video 81, 0 Jun 19 22:22 /dev/video0
83 crw-rw---- 1 root video 81, 16 Jun 19 22:22 /dev/video16
84 crw-rw---- 1 root video 81, 24 Jun 19 22:22 /dev/video24
85 crw-rw---- 1 root video 81, 32 Jun 19 22:22 /dev/video32
86 crw-rw---- 1 root video 81, 48 Jun 19 22:22 /dev/video48
87 crw-rw---- 1 root video 81, 64 Jun 19 22:22 /dev/radio0
88 crw-rw---- 1 root video 81, 224 Jun 19 22:22 /dev/vbi0
89 crw-rw---- 1 root video 81, 228 Jun 19 22:22 /dev/vbi8
90 crw-rw---- 1 root video 81, 232 Jun 19 22:22 /dev/vbi16
|
| /linux/include/linux/mfd/syscon/ |
| H A D | imx6q-iomuxc-gpr.h | 110 #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
112 #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
229 #define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
319 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
320 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
321 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
322 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
323 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
324 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
325 #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
[all …]
|
| /linux/include/dt-bindings/pinctrl/ |
| H A D | keystone.h | 18 #define BUFFER_CLASS_B (0 << 19)
19 #define BUFFER_CLASS_C (1 << 19)
20 #define BUFFER_CLASS_D (2 << 19)
21 #define BUFFER_CLASS_E (3 << 19)
|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-sdr-pcu20be.rst | 20 the 20 bits, bit 19:2 (18 bit) is data and bit 1:0 (2 bit) can be any
36 - I'\ :sub:`0[19:12]`
41 - I'\ :sub:`1[19:12]`
47 - Q'\ :sub:`0[19:12]`
52 - Q'\ :sub:`1[19:12]`
|
| /linux/arch/microblaze/include/asm/ |
| H A D | delay.h | 24 * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
28 * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
31 * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
65 __udelay((n) * (19 * HZ)); \
67 __udelay((n) * (19 * HZ)); \
|
| /linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
| H A D | tpc0_cfg_masks.h | 41 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19
107 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19
173 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19
239 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19
305 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19
371 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19
437 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19
503 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19
569 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19
635 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19
[all …]
|