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/linux/drivers/gpu/drm/exynos/
H A D	regs-gsc.h	`7 * Register definition file for Samsung G-Scaler driver 13 /* G-Scaler enable / 33 / G-Scaler S/W reset / 37 / G-Scaler IRQ / 40 #define GSC_IRQ_STATUS_OR_FRM_DONE (1 << 16) 45 / G-Scaler input control */ 51 #define GSC_IN_ROT_MASK (7 << 16) 52 #define GSC_IN_ROT_270 (7 << 16) 53 #define GSC_IN_ROT_90_YFLIP (6 << 16) 54 #define GSC_IN_ROT_90_XFLIP (5 << 16) [all …]`
/linux/drivers/media/platform/samsung/exynos-gsc/
H A D	gsc-regs.h	`6 * Register definition file for Samsung G-Scaler driver 12 /* G-Scaler enable / 18 / G-Scaler S/W reset / 22 / G-Scaler IRQ / 25 #define GSC_IRQ_STATUS_FRM_DONE_IRQ (1 << 16) 29 / G-Scaler input control */ 31 #define GSC_IN_ROT_MASK (7 << 16) 32 #define GSC_IN_ROT_270 (7 << 16) 33 #define GSC_IN_ROT_90_YFLIP (6 << 16) 34 #define GSC_IN_ROT_90_XFLIP (5 << 16) [all …]`
/linux/Documentation/dev-tools/kunit/
H A D	kunit_suitememorydiagram.svg	`3 <g transform="translate(-13.724 -17.943)"> 4 <g fill="#dad4d4" fill-opacity=".91765" stroke="#1a1a1a"> 9 </g> 10 <g> 12 …f" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="328.00888" y="446.6182… 13 </g> 14 <g transform="translate(0 -258.6)"> 16 …f" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="328.00888" y="446.6182… 17 </g> 18 <g transform="translate(0 -217.27)"> [all …]`
/linux/arch/x86/lib/
H A D	crct10dif-pcl-asm_64.S	`68 movdqu \offset+16(buf), %xmm12 95 # Assumes len >= 16. 107 movdqu 160(buf), %xmm0 108 movdqu 161(buf), %xmm1 109 movdqu 162(buf), %xmm2 110 movdqu 163(buf), %xmm3 111 movdqu 164(buf), %xmm4 112 movdqu 165(buf), %xmm5 113 movdqu 166(buf), %xmm6 114 movdqu 167(buf), %xmm7 [all …]`
/linux/arch/arm64/crypto/
H A D	polyval-ce-core.S	`18 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1. 96 ext v25.16b, X.16b, X.16b, #8 97 ext v26.16b, Y.16b, Y.16b, #8 98 eor v25.16b, v25.16b, X.16b 99 eor v26.16b, v26.16b, Y.16b 103 eor HI.16b, HI.16b, v28.16b 104 eor LO.16b, LO.16b, v29.16b 105 eor MI.16b, MI.16b, v27.16b 117 ext v25.16b, X.16b, X.16b, #8 118 ext v26.16b, Y.16b, Y.16b, #8 [all …]`
/linux/include/dt-bindings/memory/
H A D	mt8186-memory-port.h	`14 * MM IOMMU supports 16GB dma address. We separate it to four ranges: 15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 23 * disp 0 ~ 4G larb0/1/2 24 * vcodec 4G ~ 8G larb4/7 25 * cam/mdp 8G ~ 12G the other larbs. 26 * N/A 12G ~ 16G 105 #define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16) 136 #define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) 165 /* LARB 16 -- RAW-A */ [all …]`
H A D	mt8195-memory-port.h	12 * MM IOMMU supports 16GB dma address. We separate it to four ranges: 13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 21 * disp 0 ~ 4G larb0/1/2/3 22 * vcodec 4G ~ 8G larb19/20/21/22/23/24 23 * cam/mdp 8G ~ 12G the other larbs. 24 * N/A 12G ~ 16G 30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16) 138 #define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16) [all …]
H A D	mediatek,mt8188-memory-port.h	`33 #define SMI_L15_ID 16 45 * MM IOMMU supports 16GB dma address. We separate it to four ranges: 46 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 49 * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 54 * disp 0 ~ 4G larb0/1/2/3 55 * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23 56 * cam/mdp 8G ~ 12G the other larbs. 57 * N/A 12G ~ 16G 62 * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21 63 * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27 [all …]`
/linux/arch/arm64/lib/
H A D	crc-t10dif-core.S	96 * Pairwise long polynomial multiplication of two 16-bit values 115 * 2 (w0x2 ^ w1x1) << 16 ^ \| (y0z2 ^ y1z1) << 16 ^ 128 * and after performing 8x8->16 bit long polynomial multiplication of 130 * we obtain the following four vectors of 16-bit elements: 143 * (*) NOTE: the 16x64 bit polynomial multiply below is not equivalent 149 ext t7.16b, \b64\().16b, \b64\().16b, #1 150 tbl t5.16b, {\a16\().16b}, perm.16b 151 uzp1 t7.16b, \b64\().16b, t7.16b 153 ext \b64\().16b, t4.16b, t4.16b, #15 154 eor \c64\().16b, t8.16b, t5.16b [all …]
/linux/arch/x86/crypto/
H A D	polyval-clmulni_asm.S	16 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1. 45 .section .rodata.cst16.gstar, "aM", @progbits, 16 46 .align 16 67 * specified by (MSG + 16i) and (KEY_POWERS + 16i) and XORs the components of 88 movups (16\i)(MSG), %xmm0 92 vpclmulqdq $0x01, (16\i)(KEY_POWERS), %xmm0, %xmm2 93 vpclmulqdq $0x00, (16\i)(KEY_POWERS), %xmm0, %xmm1 94 vpclmulqdq $0x10, (16\i)(KEY_POWERS), %xmm0, %xmm3 95 vpclmulqdq $0x11, (16\i)(KEY_POWERS), %xmm0, %xmm4 130 This macro computes p(x) mod g(x) where p(x) is in montgomery form and g(x) = [all …]
H A D	sha256-ssse3-asm.S	`104 g = %r10d define 115 _XFER_SIZE = 16 138 h = g 139 g = f define 150 ## compute W[-16] + W[-7] 4 at a time 162 xor g, y2 # y2 = f^g 163 paddd X0, XTMP0 # XTMP0 = W[-7] + W[-16] 165 and e, y2 # y2 = (f^g)&e 171 xor g, y2 # y2 = CH = ((f^g)&e)^g 203 xor g, y2 # y2 = f^g [all …]`
H A D	sha256-avx-asm.S	`111 g = %r10d define 121 _XFER_SIZE = 16 144 h = g 145 g = f define 156 ## compute W[-16] + W[-7] 4 at a time 167 xor g, y2 # y2 = f^g 168 vpaddd X0, XTMP0, XTMP0 # XTMP0 = W[-7] + W[-16] 170 and e, y2 # y2 = (f^g)&e 176 xor g, y2 # y2 = CH = ((f^g)&e)^g 203 xor g, y2 # y2 = f^g [all …]`
H A D	sm3-avx-asm_64.S	`24 #define state_h4 16 114 #define g %r14d macro 181 #define R(i, a, b, c, d, e, f, g, h, round, widx, wtype) \ argument 199 /* GG#i(e,f,g) => t2 / \ 200 GG##i(e, f, g, t2, t1); \ 215 #define R1(a, b, c, d, e, f, g, h, round, widx, wtype) \ argument 216 R(1, a, b, c, d, e, f, g, h, round, widx, wtype) 218 #define R2(a, b, c, d, e, f, g, h, round, widx, wtype) \ argument 219 R(2, a, b, c, d, e, f, g, h, round, widx, wtype) 241 vmovdqu 016(RDATA), XTMP0; /* XTMP0: w3, w2, w1, w0 */ \ [all …]`
/linux/arch/arm/lib/
H A D	crc-t10dif-core.S	116 * Pairwise long polynomial multiplication of two 16-bit values 135 * 2 (w0x2 ^ w1x1) << 16 ^ \| (y0z2 ^ y1z1) << 16 ^ 148 * and after performing 8x8->16 bit long polynomial multiplication of 150 * we obtain the following four vectors of 16-bit elements: 253 // XOR the first 16 data bits with the initial CRC value. 275 // Now fold the 112 bytes in q0-q6 into the 16 bytes in q7. 286 // Fold across 16 bytes. 291 // Then subtract 16 to simplify the termination condition of the 293 adds len, len, #(128-16) 295 // While >= 16 data bytes remain (not counting q7), fold the 16 bytes q7 [all …]
/linux/Documentation/userspace-api/media/v4l/
H A D	pixfmt-srggb16.rst	15 16-bit Bayer formats 22 These four pixel formats are raw sRGB / Bayer formats with 16 bits per 23 sample. Each sample is stored in a 16-bit word. Each n-pixel row contains 39 - G\ :sub:`01low` 40 - G\ :sub:`01high` 43 - G\ :sub:`03low` 44 - G\ :sub:`03high` 46 - G\ :sub:`10low` 47 - G\ :sub:`10high` 50 - G\ :sub:`12low` [all …]
H A D	metafmt-vsp1-hgo.rst	31 - In 64 bins maximum mode, the HGO operates on the maximum of the (R, G, B) 36 - In 256 bins maximum mode, the HGO operates on the maximum of the (R, G, B) 52 - [23:16] 62 - G/Y/S max [7:0] 64 - G/Y/S min [7:0] 72 * - 16 73 - :cspan:`4` G/Y/S sum [31:0] 83 - :cspan:`4` G/Y/S bin 0 [31:0] 87 - :cspan:`4` G/Y/S bin 63 [31:0] 103 - [23:16] [all …]
H A D	pixfmt-srggb10.rst	16 10-bit Bayer formats expanded to 16 bits 23 sample. Each sample is stored in a 16-bit word, with 6 unused 44 - G\ :sub:`01low` 45 - G\ :sub:`01high` 48 - G\ :sub:`03low` 49 - G\ :sub:`03high` 51 - G\ :sub:`10low` 52 - G\ :sub:`10high` 55 - G\ :sub:`12low` 56 - G\ :sub:`12high` [all …]
H A D	pixfmt-srggb12.rst	17 12-bit Bayer formats expanded to 16 bits 24 colour. Each colour component is stored in a 16-bit word, with 4 unused 45 - G\ :sub:`01low` 46 - G\ :sub:`01high` 49 - G\ :sub:`03low` 50 - G\ :sub:`03high` 52 - G\ :sub:`10low` 53 - G\ :sub:`10high` 56 - G\ :sub:`12low` 57 - G\ :sub:`12high` [all …]
H A D	pixfmt-srggb14.rst	15 14-bit Bayer formats expanded to 16 bits 23 colour. Each sample is stored in a 16-bit word, with two unused high 45 - G\ :sub:`01low` 46 - G\ :sub:`01high` 49 - G\ :sub:`03low` 50 - G\ :sub:`03high` 52 - G\ :sub:`10low` 53 - G\ :sub:`10high` 56 - G\ :sub:`12low` 57 - G\ :sub:`12high` [all …]
/linux/crypto/
H A D	sm3.c	35 * Transform the message X which consists of 16 32-bit-words. See 38 #define R(i, a, b, c, d, e, f, g, h, t, w1, w2) \ argument 43 h += GG ## i(e, f, g) + ss1 + (w1); \ 49 #define R1(a, b, c, d, e, f, g, h, t, w1, w2) \ argument 50 R(1, a, b, c, d, e, f, g, h, t, w1, w2) 51 #define R2(a, b, c, d, e, f, g, h, t, w1, w2) \ argument 52 R(2, a, b, c, d, e, f, g, h, t, w1, w2) 72 static void sm3_transform(struct sm3_state sctx, u8 const data, u32 W[16]) in sm3_transform() argument 74 u32 a, b, c, d, e, f, g, h, ss1, ss2; in sm3_transform() local 82 g = sctx->state[6]; in sm3_transform() [all …]
/linux/drivers/mtd/nand/raw/
H A D	nand_ids.c	`29 {"TC58NVG0S3E 1G 3.3V 8-bit", 32 {"TC58NVG2S0F 4G 3.3V 8-bit", 35 {"TC58NVG2S0H 4G 3.3V 8-bit", 38 {"TC58NVG3S0F 8G 3.3V 8-bit", 41 {"TC58NVG5D2 32G 3.3V 8-bit", 44 {"TC58NVG6D2 64G 3.3V 8-bit", 47 {"SDTNQGAMA 64G 3.3V 8-bit", 50 {"SDTNRGAMA 64G 3.3V 8-bit", 53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", 57 {"H27UCG8T2ETR-BC 64G 3.3V 8-bit", [all …]`
/linux/include/uapi/drm/
H A D	drm_fourcc.h	106 ((__u32)(c) << 16) \| ((__u32)(d) << 24)) 149 /* 16 bpp Red (direct relationship between channel value and brightness) / 152 / 16 bpp RG / 153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') / [15:0] R:G 8:8 little endian / 154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') / [15:0] G:R 8:8 little endian / 157 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') / [31:0] R:G 16:16 little endian / 158 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') / [31:0] G:R 16:16 little endian / 161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') / [7:0] R:G:B 3:3:2 / 162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') / [7:0] B:G:R 2:3:3 / 164 / 16 bpp RGB */ [all …]
/linux/Documentation/devicetree/bindings/display/
H A D	simple-framebuffer.yaml	48 mode information and enable them. This way if e.g. later on support 97 * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b 98 * `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b 99 * `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r 100 * `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b 101 * `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b 102 * `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a 103 * `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b 104 * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b 105 * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b [all …]
/linux/drivers/gpio/
H A D	gpio-davinci.c	73 struct davinci_gpio_regs __iomem g; in irq2regs() local 75 g = (__force struct davinci_gpio_regs __iomem )irq_data_get_irq_chip_data(d); in irq2regs() 77 return g; in irq2regs() 89 struct davinci_gpio_regs __iomem g; in __davinci_direction() local 95 g = d->regs[bank]; in __davinci_direction() 97 temp = readl_relaxed(&g->dir); in __davinci_direction() 100 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction() 104 writel_relaxed(temp, &g->dir); in __davinci_direction() 131 struct davinci_gpio_regs __iomem g; in davinci_gpio_get() local 134 g = d->regs[bank]; in davinci_gpio_get() [all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A D	lan966x_regs.h	35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) argument 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) argument 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 71 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 161 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) argument 170 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) argument 193 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 272 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) argument 305 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) argument [all …]

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