Lines Matching +full:16 +full:g

14  * MM IOMMU supports 16GB dma address. We separate it to four ranges:
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
105 #define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16)
136 #define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16)
165 /* LARB 16 -- RAW-A */
166 #define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0)
167 #define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1)
168 #define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2)
169 #define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3)
170 #define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4)
171 #define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5)
172 #define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6)
173 #define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7)
174 #define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8)
175 #define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9)
176 #define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10)
177 #define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11)
178 #define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12)
179 #define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13)
180 #define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14)
181 #define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15)
182 #define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16)
201 #define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16)