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/linux/Documentation/devicetree/bindings/pci/
H A Dv3,v360epc-pci.yaml35 The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB,
36 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The
46 256MB (0x10000000) in size. The prefetchable memory window must be
72 ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>, /* 16 MiB @ LB 60000000 */
75 …dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */
83 <0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */
87 <0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */
91 <0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */
95 <0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */
/linux/arch/alpha/kernel/
H A Dcore_mcpcia.c27 * NOTE: Herein lie back-to-back mb instructions. They are magic.
72 * 23:16 bus number (8 bits = 128 possible buses)
104 mb(); in conf_read()
108 mb(); in conf_read()
113 mb(); in conf_read()
117 mb(); in conf_read()
118 mb(); /* magic */ in conf_read()
123 mb(); in conf_read()
126 mb(); in conf_read()
148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()
[all …]
H A Dsys_alcor.c42 mb(); in alcor_update_irq_hw()
48 alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); in alcor_enable_irq()
54 alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); in alcor_disable_irq()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
103 handle_irq(16 + i); in alcor_device_interrupt()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
[all …]
H A Dcore_wildfire.c107 * Window 0 is scatter-gather 8MB at 8MB (for isa) in wildfire_init_hose()
110 * Window 3 is scatter-gather 128MB at 3GB in wildfire_init_hose()
330 mb(); in wildfire_machine_check()
331 mb(); /* magic */ in wildfire_machine_check()
335 mb(); in wildfire_machine_check()
353 mb(); in wildfire_pci_tbi()
373 addr = (bus << 16) | (device_fn << 8) | where; in mk_conf_addr()
419 mb(); in wildfire_write_config()
424 mb(); in wildfire_write_config()
429 mb(); in wildfire_write_config()
[all …]
H A Dio.c20 mb(); in ioread8()
22 mb(); in ioread8()
29 mb(); in ioread16()
31 mb(); in ioread16()
38 mb(); in ioread32()
40 mb(); in ioread32()
47 mb(); in ioread64()
49 mb(); in ioread64()
55 mb(); in iowrite8()
61 mb(); in iowrite16()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
18 #define MSIX_BAR_SIZE 0x4000ull /* 16KB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
[all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A Dtlb.json47 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page."
52 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page."
57 …BriefDescription": "This event counts operations that cause a TLB access to the L1I in 512MB page."
67 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 16GB page."
82 … "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 2MB page."
87 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 32MB page."
92 …BriefDescription": "This event counts operations that cause a TLB access to the L1D in 512MB page."
102 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 16GB page."
117 … "BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 2MB page."
122 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 32MB page."
[all …]
/linux/arch/microblaze/kernel/
H A Dhead.S147 * kernel initialization. This maps the first 16 MBytes of memory 1:1
184 bgei r11, GT16 /* size is greater than 16MB */
186 bgei r11, GT8 /* size is greater than 8MB */
188 bgei r11, GT4 /* size is greater than 4MB */
189 /* size is less than 4MB */
191 bgei r11, GT2 /* size is greater than 2MB */
192 addik r9, r0, 0x0100000 /* TLB0 must be 1MB */
194 bgei r11, GT1 /* size is greater than 1MB */
198 ori r9, r0, 0x400000 /* TLB0 is 4MB */
200 GT16: /* TLB0 is 16MB */
[all …]
/linux/sound/isa/gus/
H A Dgus_io.c17 mb(); in snd_gf1_delay()
36 mb(); in __snd_gf1_ctrl_stop()
38 mb(); in __snd_gf1_ctrl_stop()
40 mb(); in __snd_gf1_ctrl_stop()
42 mb(); in __snd_gf1_ctrl_stop()
50 mb(); in __snd_gf1_write8()
52 mb(); in __snd_gf1_write8()
59 mb(); in __snd_gf1_look8()
67 mb(); in __snd_gf1_write16()
69 mb(); in __snd_gf1_write16()
[all...]
/linux/drivers/net/ethernet/apple/
H A Dmace.c73 * and another 16 bytes to allow us to align the dma command
74 * buffers on a 16 byte boundary.
305 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); in dbdma_reset()
319 volatile struct mace __iomem *mb = mp->mace; in mace_reset() local
325 out_8(&mb->biucc, SWRST); in mace_reset()
326 if (in_8(&mb->biucc) & SWRST) { in mace_reset()
337 out_8(&mb->imr, 0xff); /* disable all intrs for now */ in mace_reset()
338 i = in_8(&mb->ir); in mace_reset()
339 out_8(&mb->maccc, 0); /* turn off tx, rx */ in mace_reset()
341 out_8(&mb->biucc, XMTSP_64); in mace_reset()
[all …]
/linux/Documentation/arch/x86/x86_64/
H A Dmm.rst20 from TB to GB and then MB/KB.
22 - "16M TB" might look weird at first sight, but it's an easier way to visualize size
23 notation than "16 EB", which few will recognize at first sight as 16 exabytes.
63 ffffec0000000000 | -20 TB | fffffbffffffffff | 16 TB | KASAN shadow memory
77 …ffffffff80000000 | -2 GB | ffffffff9fffffff | 512 MB | kernel text mapping, mapped to physic…
78 ffffffff80000000 |-2048 MB | | |
79 ffffffffa0000000 |-1536 MB | fffffffffeffffff | 1520 MB | module mapping space
80 ffffffffff000000 | -16 MB | | |
81 …FIXADDR_START | ~-11 MB | ffffffffff5fffff | ~0.5 MB | kernel-internal fixmap range, variable s…
82 ffffffffff600000 | -10 MB | ffffffffff600fff | 4 kB | legacy vsyscall ABI
[all …]
/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
/linux/Documentation/fb/
H A Dmatroxfb.rst48 16 0x111 0x182 0x114 0x18A
63 16 0x117 0x192 0x11A 0x19A 0x11E
91 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
125 memory usable for on-screen display (i.e. max. 8 MB).
162 - 0 -> 2x128Kx32 chips, 2MB onboard, probably sgram
163 - 1 -> 2x128Kx32 chips, 4MB onboard, probably sgram
164 - 2 -> 2x256Kx32 chips, 4MB onboard, probably sgram
165 - 3 -> 2x256Kx32 chips, 8MB onboard, probably sgram
166 - 4 -> 2x512Kx16 chips, 8/16MB onboard, probably sdram only
168 - 6 -> 4x128Kx32 chips, 4MB onboard, probably sgram
[all …]
H A Dintel810.rst37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
41 - Full and optimized hardware acceleration at 8, 16 and 24 bpp
88 select amount of system RAM in MB to allocate for the video memory
90 Recommendation: 1 - 4 MB.
123 select at what offset in MB of the logical memory to allocate the
126 offset (16 MB for a 64 MB aperture, 8 MB for a 32 MB aperture) will
127 avoid XFree86's usage and allows up to 7 MB/15 MB of framebuffer
129 (0 for maximum usage, 31/63 MB for the least amount). Note, an
133 (default = 8 or 16 MB)
195 will use 2 MB of System RAM. MTRR support will be enabled. The refresh rate
[all …]
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c44 * | snps,dw-apb-intc (MB)| in axs10x_enable_gpio_intc_wire()
55 * DT hardware topology - connect MB intc directly to cpu intc in axs10x_enable_gpio_intc_wire()
94 char mb[32]; in axs10x_early_init() local
104 scnprintf(mb, 32, "MainBoard v%d", mb_rev); in axs10x_early_init()
105 axs10x_print_board_ver(CREG_MB_VER, mb); in axs10x_early_init()
121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
122 * of which maps to a corresponding 256MB aperture in Target slave memory map.
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * MB AXI Tunnel Master, which also has a mem map setup
133 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
[all …]
/linux/drivers/eisa/
H A Deisa.ids86 ALR3023 "ALR 16-bit VGA without Parallel port"
108 ARC0020 "Alta TokenCombo-16 S/U"
156 COG5000 "Cogent eMASTER+ AT Combo 16-Bit Workstation Ethernet Adapter"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
281 CPQ9018 "Compaq 486/33 Processor Board (8 MB)"
283 CPQ9035 "Compaq 486SX/16 Processor Board"
284 CPQ9036 "Compaq 486SX/25 Processor Board (8 MB)"
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_isr.c151 fctl = ~(abts->f_ctl[2] | 0x7F) << 16 | in qla24xx_process_abts()
155 abts_rsp->f_ctl[2] = fctl >> 16 & 0xff; in qla24xx_process_abts()
349 uint16_t mb[8]; in qla2100_intr_handler() local
393 mb[0] = RD_MAILBOX_REG(ha, reg, 0); in qla2100_intr_handler()
394 if (mb[0] > 0x3fff && mb[0] < 0x8000) { in qla2100_intr_handler()
395 qla2x00_mbx_completion(vha, mb[0]); in qla2100_intr_handler()
397 } else if (mb[0] > 0x7fff && mb[0] < 0xc000) { in qla2100_intr_handler()
398 mb[1] = RD_MAILBOX_REG(ha, reg, 1); in qla2100_intr_handler()
399 mb[2] = RD_MAILBOX_REG(ha, reg, 2); in qla2100_intr_handler()
400 mb[3] = RD_MAILBOX_REG(ha, reg, 3); in qla2100_intr_handler()
[all …]
H A Dqla_mbx.c95 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
161 mcp->mb[0] = MBS_LINK_DOWN_ERROR; in qla2x00_mailbox_command()
171 !is_rom_cmd(mcp->mb[0])) || ha->flags.eeh_busy) { in qla2x00_mailbox_command()
174 mcp->mb[0]); in qla2x00_mailbox_command()
188 mcp->mb[0]); in qla2x00_mailbox_command()
198 ha->flags.purge_mbox, ha->flags.eeh_busy, mcp->mb[0]); in qla2x00_mailbox_command()
208 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); in qla2x00_mailbox_command()
228 iptr = mcp->mb; in qla2x00_mailbox_command()
229 command = mcp->mb[0]; in qla2x00_mailbox_command()
383 mcp->mb[0] = MBS_LINK_DOWN_ERROR; in qla2x00_mailbox_command()
[all …]
/linux/arch/mips/include/asm/dec/
H A Dkn05.h7 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
23 * The oncard MB (Memory Buffer) ASIC provides an additional address
24 * decoder. Certain address ranges within the "high" 16 slots are
34 #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
35 #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
36 #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
37 #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
48 * MB ASIC interrupt bits.
57 * Bits for the MB interrupt register.
64 * Bits for the MB control & status register.
[all …]
/linux/drivers/scsi/csiostor/
H A Dcsio_mb.c49 /* MB Command/Response Helpers */
60 hdr = (struct fw_cmd_hdr *)(mbp->mb); in csio_mb_fw_retval()
80 struct fw_hello_cmd *cmdp = (struct fw_hello_cmd *)(mbp->mb); in csio_mb_hello()
86 cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); in csio_mb_hello()
112 struct fw_hello_cmd *rsp = (struct fw_hello_cmd *)(mbp->mb); in csio_mb_process_hello_rsp()
143 struct fw_bye_cmd *cmdp = (struct fw_bye_cmd *)(mbp->mb); in csio_mb_bye()
149 cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); in csio_mb_bye()
166 struct fw_reset_cmd *cmdp = (struct fw_reset_cmd *)(mbp->mb); in csio_mb_reset()
172 cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); in csio_mb_reset()
200 struct fw_params_cmd *cmdp = (struct fw_params_cmd *)(mbp->mb); in csio_mb_params()
[all …]
/linux/arch/arm64/include/asm/
H A Datomic_lse.h36 #define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \ argument
44 " " #asm_op #mb " %w[i], %w[old], %[v]" \
106 #define ATOMIC_FETCH_OP_AND(name, mb, cl...) \ argument
143 #define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \ argument
151 " " #asm_op #mb " %[i], %[old], %[v]" \
213 #define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \ argument
248 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \ argument
256 " cas" #mb #sfx " %" #w "[old], %" #w "[new], %[v]\n" \
266 __CMPXCHG_CASE(w, h, , 16, )
270 __CMPXCHG_CASE(w, h, acq_, 16, a, "memory")
[all …]
H A Datomic_ll_sc.h42 #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
55 " " #mb \
63 #define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \ argument
76 " " #mb \
138 #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
151 " " #mb \
159 #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
172 " " #mb \
239 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \ argument
263 " " #mb "\n" \
[all …]
/linux/drivers/net/can/
H A Dat91_can.c76 #define AT91_BR_BRP_MASK GENMASK(22, 16)
82 #define AT91_ECR_TEC_MASK GENMASK(23, 16)
87 #define AT91_MMR_PRIOR_MASK GENMASK(19, 16)
95 #define AT91_MSR_MDLC_MASK GENMASK(19, 16)
101 #define AT91_MCR_MDLC_MASK GENMASK(19, 16)
117 #define AT91_IRQ_ERRA BIT(16)
190 .tseg1_max = 16,
297 unsigned int mb, enum at91_mb_mode mode, in set_mb_mode_prio() argument
303 at91_write(priv, AT91_MMR(mb), reg_mmr); in set_mb_mode_prio()
306 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, in set_mb_mode() argument
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dgio.h20 * There is 10MB of GIO address space for GIO64 slot devices
23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
46 * bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
60 * 0x07 16 bit SCSI Card [*]
/linux/Documentation/arch/arm/
H A Dixp4xx.rst69 The IXP4xx family allows for up to 256MB of memory but the PCI interface
70 can only expose 64MB of that memory to the PCI bus. This means that if
71 you are running with > 64MB, all PCI buffers outside of the accessible
78 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
82 limits the system to just 64MB of PCI memory. This can be
85 2) If > 64MB of memory space is required, the IXP4xx can be
87 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
125 also known as the Richfield board. It contains 4 PCI slots, 16MB
132 of just 16.
148 contains a CPU and 16MB of flash on the board and needs to be

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