| /linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_h264_dec.c | 28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
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| H A D | hantro_g1_mpeg2_dec.c | 20 #define G1_REG_REFER1_BASE G1_SWREG(15)
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
[all …]
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| H A D | rockchip_vpu2_hw_mpeg2_dec.c | 23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
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| /linux/lib/crypto/ |
| H A D | blake2b.c | 21 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
22 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
23 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
24 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
25 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
26 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
27 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
28 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
29 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
30 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
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| H A D | blake2s.c | 21 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
22 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
23 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
24 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
25 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
26 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
27 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
28 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
29 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
30 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
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| /linux/tools/perf/util/ |
| H A D | blake2s.c | 13 static inline u32 ror32(u32 v, int n) in ror32() argument
15 return (v >> n) | (v << (32 - n)); in ror32()
31 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
32 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
33 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
34 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
35 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
36 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
37 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
38 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
[all …]
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| /linux/lib/crypto/arm/ |
| H A D | blake2s-core.S | 116 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
118 // spilling v[8..9], then to v[10..15], then to the message block. r10-r12 and
135 // (v[0], v[4], v[8], v[12]) and (v[1], v[5], v[9], v[13]).
136 __ldrd r10, r11, sp, 16 // load v[12] and v[13]
143 // (v[2], v[6], v[10], v[14]) and (v[3], v[7], v[11], v[15]).
144 __ldrd r8, r9, sp, 8 // load v[10] and v[11]
145 __ldrd r10, r11, sp, 24 // load v[14] and v[15]
148 str r10, [sp, #24] // store v[14]
149 // v[10], v[11], and v[15] are used below, so no need to store them yet.
155 // (v[0], v[5], v[10], v[15]) and (v[1], v[6], v[11], v[12]).
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| H A D | blake2b-neon-core.S | 66 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
76 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
77 // (v[2], v[6], v[10], v[14]), and (v[3], v[7], v[11], v[15]).
148 // (v[0], v[5], v[10], v[15]), (v[1], v[6], v[11], v[12]),
149 // (v[2], v[7], v[8], v[13]), and (v[3], v[4], v[9], v[14]).
277 // 'v'. Fortunately, there are exactly enough NEON registers to fit the
278 // entire state matrix in q0-q7 and the entire message block in q8-15.
288 veor q6, q6, q14 // v[12..13] = IV[4..5] ^ t[0..1]
290 veor q7, q7, q15 // v[14..15] = IV[6..7] ^ f[0..1]
298 _blake2b_round 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | regs-scaler.h | 56 * 1 70 74 78 7c 150 154 158 15c
158 #define SCALER_INT_EN_ILLEGAL_DST_CB_BASE (1 << 15)
186 #define SCALER_INT_STATUS_ILLEGAL_DST_CB_BASE (1 << 15)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
222 #define SCALER_L8 15
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
239 #define SCALER_SRC_Y_POS_GET_YV_POS(r) SCALER_GET(r, 15, 0)
[all …]
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| /linux/drivers/video/fbdev/ |
| H A D | atafb_iplan2p8.c | 53 if (!((sx ^ dx) & 15)) { in atafb_iplan2p8_copyarea()
57 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
58 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
59 if (sx & 15) { in atafb_iplan2p8_copyarea()
78 if (width & 15) in atafb_iplan2p8_copyarea()
82 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
83 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
85 if ((sx + width) & 15) { in atafb_iplan2p8_copyarea()
104 if (sx & 15) in atafb_iplan2p8_copyarea()
113 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
[all …]
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| H A D | atafb_iplan2p4.c | 46 if (!((sx ^ dx) & 15)) { in atafb_iplan2p4_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
52 if (sx & 15) { in atafb_iplan2p4_copyarea()
71 if (width & 15) in atafb_iplan2p4_copyarea()
75 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
76 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
78 if ((sx + width) & 15) { in atafb_iplan2p4_copyarea()
97 if (sx & 15) in atafb_iplan2p4_copyarea()
106 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local
[all …]
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| H A D | valkyriefb.h | 8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
101 15,
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
107 /* Register values for 1024x768, 72Hz mode (15) */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
110 * caused the 15" Apple Studio Display to not work in this mode. While this
117 15,
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
[all …]
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| H A D | atafb_iplan2p2.c | 46 if (!((sx ^ dx) & 15)) { in atafb_iplan2p2_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
52 if (sx & 15) { in atafb_iplan2p2_copyarea()
71 if (width & 15) in atafb_iplan2p2_copyarea()
75 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
76 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
78 if ((sx + width) & 15) { in atafb_iplan2p2_copyarea()
97 if (sx & 15) in atafb_iplan2p2_copyarea()
106 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local
[all …]
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| /linux/drivers/net/ethernet/altera/ |
| H A D | altera_msgdmahw.h | 19 * bit 15:0 sequence number
22 * bit 15:0 read stride
39 #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
105 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) argument
106 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1) argument
107 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2) argument
108 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3) argument
[all …]
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| /linux/drivers/staging/media/sunxi/cedrus/ |
| H A D | cedrus_regs.h | 13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
64 #define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s) SHIFT_AND_MASK_BITS(s, 15, 0)
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
[all …]
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| /linux/arch/x86/include/asm/ |
| H A D | perf_event_p4.h | 40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
62 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) argument
63 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) argument
81 #define p4_config_pack_escr(v) (((u64)(v)) << 32) argument
82 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
83 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) argument
84 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
86 #define p4_config_unpack_emask(v) \ argument
[all …]
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | adi,max98396.yaml | 13 The MAX98396 is a mono Class-DG speaker amplifier with I/V sense.
28 description: A 1.8V supply that powers up the AVDD pin.
31 description: A 1.2V supply that powers up the DVDD pin.
34 description: A 1.2V or 1.8V supply that powers up the VDDIO pin.
37 description: A 3.0V to 20V supply that powers up the PVDD pin.
40 description: A 3.3V to 5.5V supply that powers up the VBAT pin.
46 maximum: 15
53 maximum: 15
60 maximum: 15
69 maximum: 15
[all …]
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| H A D | cs35l32.txt | 25 3 = Boost voltage fixed at 5 V.
31 2 = (Default) left/right channels VMON[15:0], IMON [15:0].
40 0 = 3.1V
41 1 = 3.2V
42 2 = 3.3V (Default)
43 3 = 3.4V
46 0 = 3.1V
47 1 = 3.2V
48 2 = 3.3V
49 3 = 3.4V (Default)
[all …]
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| /linux/sound/ppc/ |
| H A D | snd_ps3_reg.h | 72 31 24 23 16 15 8 7 0
95 31 24 23 16 15 8 7 0
105 31 24 23 16 15 8 7 0
124 31 24 23 16 15 8 7 0
149 #define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */
154 31 24 23 16 15 8 7 0
184 31 24 23 16 15 8 7 0
224 31 24 23 16 15 8 7 0
235 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */
236 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */
[all …]
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| /linux/lib/crypto/x86/ |
| H A D | blake2s-core.S | 28 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
29 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
30 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
31 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
32 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
33 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
34 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
35 .byte 13, 7, 12, 3, 11, 14, 1, 9, 2, 5, 15, 8, 10, 0, 4, 6
36 .byte 6, 14, 11, 0, 15, 9, 3, 8, 10, 12, 13, 1, 5, 2, 7, 4
37 .byte 10, 8, 7, 1, 2, 4, 6, 5, 13, 15, 9, 3, 0, 11, 14, 12
[all …]
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| /linux/drivers/iio/adc/ |
| H A D | stm32-dfsdm.h | 52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) argument
54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) argument
56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) argument
58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) argument
60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) argument
62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) argument
64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) argument
65 #define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) argument
68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) argument
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| /linux/drivers/net/ethernet/wangxun/libwx/ |
| H A D | wx_vf.h | 23 #define WX_VXMRQC_RSS_HASH(f) FIELD_PREP(GENMASK(15, 13), f)
33 #define WX_VXRETA(i) (0xC0 + ((i) * 4)) /* i=[0,15] */
48 #define wx_conf_size(v, mwidth, uwidth) ({ \ argument
49 typeof(v) _v = (v); \
52 #define wx_buf_len(v) wx_conf_size(v, 13, 7) argument
53 #define wx_hdr_sz(v) wx_conf_size(v, 10, 6) argument
54 #define wx_buf_sz(v) wx_conf_size(v, 14, 10) argument
55 #define wx_pkt_thresh(v) wx_conf_size(v, 4, 0) argument
74 #define WX_VXRXDCTL_HDRSZ_MASK GENMASK(15, 12)
75 #define WX_VXRXDCTL_HDRSZ(f) FIELD_PREP(GENMASK(15, 12), f)
|
| /linux/drivers/media/radio/ |
| H A D | radio-tea5777.c | 83 #define TEA5777_W_FM_FORCEMONO_MASK (1LL << 15)
84 #define TEA5777_W_FM_FORCEMONO_SHIFT 15
112 #define TEA5777_W_AM_CALLIGN_MASK (1LL << 15)
113 #define TEA5777_W_AM_CALLIGN_SHIFT 15
127 #define TEA5777_R_BLIM_MASK (0x01 << 15)
128 #define TEA5777_R_BLIM_SHIFT 15
255 struct v4l2_capability *v) in vidioc_querycap() argument
259 strscpy(v->driver, tea->v4l2_dev->name, sizeof(v->driver)); in vidioc_querycap()
260 strscpy(v->card, tea->card, sizeof(v->card)); in vidioc_querycap()
261 strlcat(v->card, " TEA5777", sizeof(v->card)); in vidioc_querycap()
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| /linux/drivers/memory/ |
| H A D | renesas-rpc-if-regs.h | 35 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) argument
56 #define RPCIF_DRENR_DME BIT(15)
59 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) argument
60 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) argument
86 #define RPCIF_SMENR_DME BIT(15)
89 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8) argument
90 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4) argument
91 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0) argument
103 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) argument
106 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12) argument
[all …]
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| /linux/sound/hda/codecs/realtek/ |
| H A D | alc269.c | 466 alc_update_coef_idx(codec, 0x3b, 1<<15, 0); in alc256_init()
494 alc_update_coefex_idx(codec, 0x53, 0x02, 0x8000, 1 << 15); /* Clear bit */ in alc256_init()
495 alc_update_coefex_idx(codec, 0x53, 0x02, 0x8000, 0 << 15); in alc256_init()
548 alc_update_coef_idx(codec, 0x3b, 1<<15, 1<<15); in alc256_shutup()
562 alc_update_coef_idx(codec, 0x4a, 1<<15, 1<<15); /* Reset HP JD */ in alc285_hp_init()
605 alc_update_coef_idx(codec, 0x4a, 1<<15, 0); in alc285_hp_init()
1374 * HP Laptop 15-fd0xxx (SSID 103c:8bb6) Speaker Mute LED fix in alc285_fixup_hp_gpio_led()
1462 alc_update_coef_idx(codec, 0x4a, BIT(15), in alc245_fixup_hp_x360_amp()
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