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/linux/drivers/gpu/drm/amd/display/dc/dml/dsc/
H A Dqp_tables.h35 { 9, { 0, 2, 3, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 11, 13} },
36 { 9.5, { 0, 2, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 11, 13} },
43 { 13, { 0, 1, 2, 2, 4, 4, 4, 5, 5, 6, 6, 6, 8, 8, 9} },
62 { 6, { 4, 6, 8, 8, 9, 9, 9, 10, 11, 12, 12, 12, 12, 13, 15} },
63 { 6.5, { 4, 6, 7, 8, 8, 8, 9, 10, 11, 11, 12, 12, 12, 13, 15} },
64 { 7, { 4, 5, 7, 7, 8, 8, 8, 9, 10, 11, 11, 12, 12, 13, 14} },
65 { 7.5, { 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 14} },
66 { 8, { 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 10, 11, 11, 12, 13} },
67 { 8.5, { 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 10, 11, 11, 12, 13} },
68 { 9, { 3, 4, 5, 6, 7, 7, 7, 8, 9, 9, 10, 10, 11, 11, 13} },
[all …]
/linux/drivers/video/logo/
H A Dlogo_parisc_clut224.ppm414 236 174 8 254 198 2 246 190 13 202 152 2
1110 253 207 3 253 202 2 87 61 13 2 2 2
1129 230 230 231 186 150 74 248 183 3 254 202 13
1149 184 176 158 218 159 3 254 186 7 254 202 13
1150 253 207 3 253 202 2 253 202 2 246 190 13
1160 2 2 2 2 2 2 2 2 10 87 61 13
1169 213 150 7 236 174 8 254 194 14 254 202 13
1170 254 202 13 253 202 2 254 198 2 254 198 2
1189 248 184 12 254 190 11 254 198 13 254 198 13
1190 254 198 13 254 198 6 254 198 6 254 198 2
[all …]
H A Dlogo_spe_clut224.ppm56 9 9 11 3 3 6 104 96 81 179 179 179 122 122 122 13 13 13
76 0 0 0 5 5 5 63 63 63 24 24 24 152 149 142 175 122 13
77 238 184 12 220 170 13 226 181 52 112 86 32 194 165 151 46 46 47
83 0 0 0 5 5 5 59 59 59 21 21 21 175 122 13 231 174 11
84 240 192 13 237 183 61 240 192 13 240 192 13 234 179 16 81 64 9
91 240 192 13 240 192 13 240 192 13 215 161 11 207 152 19 81 64 9
98 220 170 13 201 147 20 189 138 9 198 154 46 199 182 125 70 70 70
105 175 122 13 175 122 13 178 151 83 192 191 189 233 233 233 179 179 179
173 0 0 0 4 4 4 39 39 39 42 42 43 19 19 21 13 13 13
187 0 0 0 13 13 13 59 59 59 2 2 6 9 9 12 56 56 56
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32f429.c67 STM32_FUNCTION(13, "OTG_HS_SOF"),
163 PINCTRL_PIN(13, "PA13"),
247 STM32_FUNCTION(13, "FMC_SDCKE1"),
259 STM32_FUNCTION(13, "FMC_SDNE1"),
270 STM32_FUNCTION(13, "FMC_NL"),
283 STM32_FUNCTION(13, "SDIO_D4"),
297 STM32_FUNCTION(13, "SDIO_D5"),
338 STM32_FUNCTION(13, "OTG_HS_ID"),
363 STM32_FUNCTION(13, "OTG_HS_DM"),
375 STM32_FUNCTION(13, "OTG_HS_DP"),
[all …]
H A Dpinctrl-stm32f746.c73 STM32_FUNCTION(13, "OTG_HS_SOF"),
112 STM32_FUNCTION(13, "FMC_SDNWE"),
174 PINCTRL_PIN(13, "PA13"),
264 STM32_FUNCTION(13, "FMC_SDCKE1"),
278 STM32_FUNCTION(13, "FMC_SDNE1"),
289 STM32_FUNCTION(13, "FMC_NL"),
302 STM32_FUNCTION(13, "SDMMC1_D4"),
316 STM32_FUNCTION(13, "SDMMC1_D5"),
357 STM32_FUNCTION(13, "OTG_HS_ID"),
381 STM32_FUNCTION(13, "OTG_HS_DM"),
[all …]
H A Dpinctrl-stm32f469.c70 STM32_FUNCTION(13, "OTG_HS_SOF"),
110 STM32_FUNCTION(13, "FMC_SDNWE"),
170 PINCTRL_PIN(13, "PA13"),
256 STM32_FUNCTION(13, "FMC_SDCKE1"),
270 STM32_FUNCTION(13, "FMC_SDNE1"),
281 STM32_FUNCTION(13, "FMC_NL"),
294 STM32_FUNCTION(13, "SDIO_D4"),
308 STM32_FUNCTION(13, "SDIO_D5"),
351 STM32_FUNCTION(13, "OTG_HS_ID"),
376 STM32_FUNCTION(13, "OTG_HS_DM"),
[all …]
H A Dpinctrl-stm32f769.c49 STM32_FUNCTION(13, "MDIOS_MDIO"),
75 STM32_FUNCTION(13, "OTG_HS_SOF"),
102 STM32_FUNCTION(13, "MDIOS_MDC"),
118 STM32_FUNCTION(13, "FMC_SDNWE"),
132 STM32_FUNCTION(13, "UART7_RX"),
157 STM32_FUNCTION(13, "MDIOS_MDIO"),
191 PINCTRL_PIN(13, "PA13"),
215 STM32_FUNCTION(13, "UART7_TX"),
268 STM32_FUNCTION(13, "UART7_RX"),
283 STM32_FUNCTION(13, "UART7_TX"),
[all …]
H A Dpinctrl-stm32h743.c54 STM32_FUNCTION(13, "MDIOS_MDIO"),
82 STM32_FUNCTION(13, "OTG_HS_SOF"),
111 STM32_FUNCTION(13, "TIM1_BKIN_COMP12"),
127 STM32_FUNCTION(13, "FMC_SDNWE"),
142 STM32_FUNCTION(13, "TIM8_BKIN2_COMP12"),
174 STM32_FUNCTION(13, "LCD_B4"),
212 PINCTRL_PIN(13, "PA13"),
328 STM32_FUNCTION(13, "FMC_SDCKE1"),
348 STM32_FUNCTION(13, "FMC_SDNE1"),
366 STM32_FUNCTION(13, "FMC_NL"),
[all …]
H A Dpinctrl-stm32mp135.c23 STM32_FUNCTION(13, "ETH2_MII_CRS"),
60 STM32_FUNCTION(13, "ETH2_MII_COL"),
73 STM32_FUNCTION(13, "SAI1_SCK_A"),
100 STM32_FUNCTION(13, "SAI2_SCK_A"),
114 STM32_FUNCTION(13, "SAI2_SD_A"),
130 STM32_FUNCTION(13, "FMC_A21"),
173 STM32_FUNCTION(13, "FMC_A7"),
179 PINCTRL_PIN(13, "PA13"),
207 STM32_FUNCTION(13, "FMC_A9"),
251 STM32_FUNCTION(13, "FMC_A6"),
[all …]
/linux/arch/arm/mach-rpc/
H A Dirq.c20 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
21 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
24 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
25 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
28 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
29 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
32 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
33 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
/linux/include/linux/mfd/wm831x/
H A Dregulator.h220 #define WM831X_DC2_OV_STS_SHIFT 13 /* DC2_OV_STS */
350 #define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */
351 #define WM831X_DC1_ON_SLOT_SHIFT 13 /* DC1_ON_SLOT - [15:13] */
352 #define WM831X_DC1_ON_SLOT_WIDTH 3 /* DC1_ON_SLOT - [15:13] */
363 #define WM831X_DC1_SLP_SLOT_MASK 0xE000 /* DC1_SLP_SLOT - [15:13] */
364 #define WM831X_DC1_SLP_SLOT_SHIFT 13 /* DC1_SLP_SLOT - [15:13] */
365 #define WM831X_DC1_SLP_SLOT_WIDTH 3 /* DC1_SLP_SLOT - [15:13] */
434 #define WM831X_DC2_ON_SLOT_MASK 0xE000 /* DC2_ON_SLOT - [15:13] */
435 #define WM831X_DC2_ON_SLOT_SHIFT 13 /* DC2_ON_SLOT - [15:13] */
436 #define WM831X_DC2_ON_SLOT_WIDTH 3 /* DC2_ON_SLOT - [15:13] */
[all …]
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S224 vmulouw 13, 8, 0
231 vaddudm 14, 14, 13 # x0
235 vmulouw 13, 8, 1
237 vaddudm 15, 15, 13 # x1
244 vmulouw 13, 8, 2
246 vaddudm 16, 16, 13 # x2
253 vmulouw 13, 8, 3
255 vaddudm 17, 17, 13 # x3
262 vmulouw 13, 8, 26
264 vaddudm 18, 18, 13 # x4
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3506.c51 RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
79 RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
95 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
124 RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
138 RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
143 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
144 RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
145 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
146 RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
147 RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
[all …]
H A Drst-rk3576.c50 RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
86 RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
104 RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13),
109 RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
110 RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
111 RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
112 RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
113 RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4),
114 RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6),
115 RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor-quackingstick-r0.dts19 qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>;
20 qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>;
/linux/Documentation/admin-guide/acpi/
H A Dfan_performance_states.rst22 -r--r--r-- 1 root root 4096 Dec 13 20:38 state0
23 -r--r--r-- 1 root root 4096 Dec 13 20:38 state1
24 -r--r--r-- 1 root root 4096 Dec 13 20:38 state10
25 -r--r--r-- 1 root root 4096 Dec 13 20:38 state11
26 -r--r--r-- 1 root root 4096 Dec 13 20:38 state2
27 -r--r--r-- 1 root root 4096 Dec 13 20:38 state3
28 -r--r--r-- 1 root root 4096 Dec 13 20:38 state4
29 -r--r--r-- 1 root root 4096 Dec 13 20:38 state5
30 -r--r--r-- 1 root root 4096 Dec 13 20:38 state6
31 -r--r--r-- 1 root root 4096 Dec 13 20:38 state7
[all …]
/linux/include/dt-bindings/memory/
H A Dmediatek,mt6893-memory-port.h20 * cam/mdp 8G ~ 12G larb9/11/13/14/16/17/18/19/20
41 #define M4U_PORT_L0_DISP_UFBC_WDMA0 MTK_M4U_DOM_ID(0, 13)
58 #define M4U_PORT_L1_DISP_UFBC_WDMA1 MTK_M4U_DOM_ID(1, 13)
110 #define M4U_PORT_L7_VENC_NBM_WDMA_DISP MTK_M4U_DOM_ID(7, 13)
141 #define M4U_PORT_L9_IMG_UFBC_W0_MDP MTK_M4U_DOM_ID(9, 13)
174 #define M4U_PORT_L11_IMG_UFBC_W0_DISP MTK_M4U_DOM_ID(11, 13)
194 #define M4U_PORT_L13_CAM_MRAWI_MDP MTK_M4U_DOM_ID(13, 0)
195 #define M4U_PORT_L13_CAM_MRAWO0_MDP MTK_M4U_DOM_ID(13, 1)
196 #define M4U_PORT_L13_CAM_MRAWO1_MDP MTK_M4U_DOM_ID(13, 2)
197 #define M4U_PORT_L13_CAM_CAMSV1_MDP MTK_M4U_DOM_ID(13, 3)
[all …]
H A Dmt8192-larb-port.h21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
94 #define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13)
113 #define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13)
132 #define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13)
149 #define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0)
150 #define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1)
151 #define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2)
152 #define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3)
153 #define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4)
154 #define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5)
[all …]
/linux/sound/soc/codecs/
H A Drt5651.h231 #define RT5651_M_DAC_L2_VOL (0x1 << 13)
232 #define RT5651_M_DAC_L2_VOL_SFT 13
271 #define RT5651_M_STO1_ADC_L2 (0x1 << 13)
272 #define RT5651_M_STO1_ADC_L2_SFT 13
289 #define RT5651_M_STO2_ADC_L2 (0x1 << 13)
290 #define RT5651_M_STO2_ADC_L2_SFT 13
325 #define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
326 #define RT5651_DAC_L1_STO_L_VOL_SFT 13
351 #define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
352 #define RT5651_DAC_DD_L1_VOL_SFT 13
[all …]
H A Drt5616.h244 #define RT5616_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
245 #define RT5616_DAC_L1_STO_L_VOL_SFT 13
262 #define RT5616_STO_DD_L1_VOL_MASK (0x1 << 13)
263 #define RT5616_DAC_DD_L1_VOL_SFT 13
290 #define RT5616_M_DAC_L2_DAC_L (0x1 << 13)
291 #define RT5616_M_DAC_L2_DAC_L_SFT 13
359 #define RT5616_G_LN_L2_RM_L_MASK (0x7 << 13)
360 #define RT5616_G_IN_L2_RM_L_SFT 13
369 #define RT5616_G_BST1_RM_L_MASK (0x7 << 13)
370 #define RT5616_G_BST1_RM_L_SFT 13
[all …]
H A Drt5640.h239 #define RT5640_M_DAC_L2_VOL (0x1 << 13)
240 #define RT5640_M_DAC_L2_VOL_SFT 13
267 #define RT5640_M_ADC_L2 (0x1 << 13)
268 #define RT5640_M_ADC_L2_SFT 13
286 #define RT5640_M_MONO_ADC_L2 (0x1 << 13)
287 #define RT5640_M_MONO_ADC_L2_SFT 13
324 #define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
325 #define RT5640_DAC_L1_STO_L_VOL_SFT 13
346 #define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
347 #define RT5640_DAC_L1_MONO_L_VOL_SFT 13
[all …]
H A Drt5670.h287 #define RT5670_M_DAC_L2_VOL (0x1 << 13)
288 #define RT5670_M_DAC_L2_VOL_SFT 13
329 #define RT5670_M_ADC_L2 (0x1 << 13)
330 #define RT5670_M_ADC_L2_SFT 13
351 #define RT5670_M_MONO_ADC_L2 (0x1 << 13)
352 #define RT5670_M_MONO_ADC_L2_SFT 13
401 #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
402 #define RT5670_DAC_L1_STO_L_VOL_SFT 13
427 #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
428 #define RT5670_DAC_L1_MONO_L_VOL_SFT 13
[all …]
H A Drt1015.h188 #define RT1015_PLL_SEL_MASK (0x1 << 13)
189 #define RT1015_PLL_SEL_SFT 13
190 #define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13)
191 #define RT1015_PLL_SEL_BCLK (0x1 << 13)
233 #define RT1015_DAC_CLK (0x1 << 13)
234 #define RT1015_DAC_CLK_BIT 13
262 #define RT1015_I2S_TCON_DF_MASK (0x7 << 13)
263 #define RT1015_I2S_TCON_DF_SFT 13
264 #define RT1015_I2S_TCON_DF_I2S (0x0 << 13)
265 #define RT1015_I2S_TCON_DF_LEFT (0x1 << 13)
[all …]
H A Drt5645.h285 #define RT5645_M_DAC_L2_VOL (0x1 << 13)
286 #define RT5645_M_DAC_L2_VOL_SFT 13
329 #define RT5645_M_ADC_L2 (0x1 << 13)
330 #define RT5645_M_ADC_L2_SFT 13
349 #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
350 #define RT5645_M_MONO_ADC_L2_SFT 13
397 #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
398 #define RT5645_DAC_L1_STO_L_VOL_SFT 13
427 #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
428 #define RT5645_DAC_L1_MONO_L_VOL_SFT 13
[all...]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8196.c47 PIN_FIELD_BASE(9, 9, 9, 0x0120, 0x10, 13, 1),
51 PIN_FIELD_BASE(13, 13, 6, 0x0120, 0x10, 3, 1),
191 PIN_FIELD_BASE(153, 153, 4, 0x00d0, 0x10, 13, 1),
192 PIN_FIELD_BASE(154, 154, 4, 0x00d0, 0x10, 13, 1),
224 PIN_FIELD_BASE(186, 186, 13, 0x0110, 0x10, 14, 1),
225 PIN_FIELD_BASE(187, 187, 13, 0x0110, 0x10, 14, 1),
226 PIN_FIELD_BASE(188, 188, 13, 0x0110, 0x10, 4, 1),
227 PIN_FIELD_BASE(189, 189, 13, 0x0110, 0x10, 9, 1),
228 PIN_FIELD_BASE(190, 190, 13, 0x0110, 0x10, 5, 1),
229 PIN_FIELD_BASE(191, 191, 13, 0x0110, 0x10, 10, 1),
[all …]

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