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Searched +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/hwtracing/intel_th/
H A Dpti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Intel Corporation.
25 unsigned int mode; member
27 unsigned int clkdiv; member
33 /* map PTI widths to MODE settings of PTI_CTL register */
35 0, 4, 8, 0, 12, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0,
46 return -EINVAL; in pti_width_mode()
54 return scnprintf(buf, PAGE_SIZE, "%d\n", pti_mode[pti->mode]); in mode_show()
72 pti->mode = ret; in mode_store()
77 static DEVICE_ATTR_RW(mode);
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/linux/drivers/pwm/
H A Dpwm-tiehrpwm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
23 #define TBCTL_PRDLD_MASK BIT(3)
25 #define TBCTL_PRDLD_IMDT BIT(3)
26 #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
27 BIT(8) | BIT(7))
28 #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
30 #define TBCTL_CTRMODE_DOWN BIT(0)
31 #define TBCTL_CTRMODE_UPDOWN BIT(1)
32 #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
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/linux/sound/soc/codecs/
H A Dadau1701.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
93 #define ADAU1701_SERICTL_INV_BCLK BIT(3)
94 #define ADAU1701_SERICTL_INV_LRCLK BIT(4)
99 #define ADAU1707_CLKDIV_UNSET (-1U)
115 u8 pin_config[12];
191 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_write()
193 return -EINVAL; in adau1701_reg_write()
198 for (i = size + 1; i >= 2; --i) { in adau1701_reg_write()
209 return -EIO; in adau1701_reg_write()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
49 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
90 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
98 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
111 #define EVTMODE BIT(5) /* Video event mode enable, tc35876x only */
117 #define VFUEN_EN BIT(0) /* Upload Enable */
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
63 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
65 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
77 /* display mode change control register except exynos4 */
85 #define LCD_WR_SETUP(x) ((x) << 12)
194 u32 clkdiv; member
202 { .compatible = "samsung,s3c6400-fimd",
204 { .compatible = "samsung,s5pv210-fimd",
206 { .compatible = "samsung,exynos3250-fimd",
208 { .compatible = "samsung,exynos4210-fimd",
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/linux/drivers/gpu/drm/tilcdc/
H A Dtilcdc_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
65 struct drm_device *dev = crtc->dev; in set_scanout()
66 struct tilcdc_drm_private *priv = dev->dev_private; in set_scanout()
73 start = gem->dma_addr + fb->offsets[0] + in set_scanout()
74 crtc->y * fb->pitches[0] + in set_scanout()
75 crtc->x * fb->format->cpp[0]; in set_scanout()
77 end = start + (crtc->mode.vdisplay * fb->pitches[0]); in set_scanout()
84 if (priv->rev == 1) in set_scanout()
85 end -= 1; in set_scanout()
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/linux/drivers/hwmon/
H A Dltc4282.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
15 #include <linux/hwmon-sysfs.h>
29 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0)
30 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1)
31 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2)
32 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5)
33 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6)
39 #define LTC4282_OV_FAULT_MASK BIT(0)
40 #define LTC4282_UV_FAULT_MASK BIT(1)
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/linux/drivers/video/fbdev/
H A Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
83 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
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/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h1 // SPDX-License-Identifier: ISC
49 /* gpio - cleared only by power-on-reset */
79 u32 clkdiv; /* corerev >= 3 */ member
234 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
251 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
262 #define CC_SR_CTL0_ENABLE_MASK BIT(0)
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
174 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
296 #define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
321 #define SSB_PMURES_4312_BB_PLL_FILTBYP 12
338 #define SSB_PMURES_4325_LNLDO4_PU 12
362 #define SSB_PMURES_4328_BG_FILTBYP 12
384 #define SSB_PMURES_5354_BG_FILTBYP 12
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/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
106 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
107 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Daiutils.c73 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
90 /* 43224 chip-specific ChipControl register bits */
92 /* 12 mA drive strength */
94 /* 12 mA drive strength for later 43224s */
109 /* 4331 chip-specific ChipControl register bits */
116 /* sprom/gpio13-15 mux */
147 /* 4319 chip-specific ChipStatus register bits */
162 /* gpio [8], sdio/usb mode */
178 /* 4336 chip-specific ChipStatus register bits */
194 /* 4313 chip-specific ChipStatus register bits */
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/linux/drivers/mmc/host/
H A Dmmci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
47 #define DRIVER_NAME "mmci-pl18x"
274 .stm32_idmabsize_mask = GENMASK(12, 5),
275 .stm32_idmabsize_align = BIT(5),
303 .stm32_idmabsize_align = BIT(5),
332 .stm32_idmabsize_align = BIT(6),
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/linux/drivers/tty/serial/
H A Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
35 #include <linux/dma-mapping.h>
54 #define UART_DUMMY_DR_RX BIT(16)
82 /* The size of the array - must be last */
261 unsigned int fifosize; /* vendor-specific */
262 unsigned int fixed_baud; /* vendor-set fixed baud rate */
263 char type[12];
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dt3_hw.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
41 * t3_wait_op_done_val - wait until an operation is completed
44 * @mask: a single-bit field within @reg that indicates completion
50 * Wait until an operation is completed by checking a bit in a register
53 * operation completes and -EAGAIN otherwise.
67 if (--attempts == 0) in t3_wait_op_done_val()
68 return -EAGAIN; in t3_wait_op_done_val()
75 * t3_write_regs - write a bunch of registers
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/linux/drivers/media/usb/gspca/
H A Dsonixj.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009-2011 Jean-François Moine <http://moinejf.free.fr>
17 MODULE_AUTHOR("Jean-François Moine <http://moinejf.free.fr>");
103 #define SCL_SEL_OD 0x20 /* open-drain mode */
301 /* sequence specific to the sensors - !! index = SENSOR_xxx */
616 {0xb1, 0x5c, 0x06, 0x00, 0x00, 0x00, 0x00, 0x10}, /* op mode ctrl */
627 {0xb1, 0x5c, 0x20, 0x00, 0x00, 0x00, 0x00, 0x10}, /* read mode */
646 /* factory mode */
652 /* auto-exposure speed (0) / white balance mode (auto RGB) */
654 * set color mode */
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