Searched +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode (Results 1 – 8 of 8) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/iio/frequency/ |
| H A D | adf4350.txt | 4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
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| H A D | adi,adf4350.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
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| /freebsd/sys/dev/bhnd/cores/chipc/ |
| H A D | chipcreg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
72 #define CHIPC_SFLASH_SIZE 12
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
97 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */
100 /* clock control registers (non-PMU devices) */
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| /freebsd/tools/tools/cxgbtool/ |
| H A D | reg_defs_t3.c | 5 /* This file is automatically generated --- do not edit */
72 { "RspQ4Disabled", 12, 1 },
101 { "LoCtlDrbDropErr", 12, 1 },
116 { "LoCtlDrbDropErr", 12, 1 },
150 { "WFParErr", 12, 2 },
167 { "WFParErr", 12, 2 },
195 { "64Bit", 0, 1 },
204 { "ZPUMan", 12, 3 },
220 { "MSIXParErr", 12, 3 },
235 { "MSIXParErr", 12, 3 },
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| H A D | reg_defs_t3b.c | 4 /* This file is automatically generated --- do not edit */
79 { "RspQ4Disabled", 12, 1 },
111 { "LoCtlDrbDropErr", 12, 1 },
126 { "LoCtlDrbDropErr", 12, 1 },
160 { "WFParErr", 12, 2 },
177 { "WFParErr", 12, 2 },
205 { "64Bit", 0, 1 },
214 { "ZPUMan", 12, 3 },
230 { "MSIXParErr", 12, 3 },
245 { "MSIXParErr", 12, 3 },
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| H A D | reg_defs_t3c.c | 4 /* This file is automatically generated --- do not edit */
82 { "RspQ4Disabled", 12, 1 },
126 { "LoCtlDrbDropErr", 12, 1 },
153 { "LoCtlDrbDropErr", 12, 1 },
187 { "WFParErr", 12, 2 },
204 { "WFParErr", 12, 2 },
233 { "64Bit", 0, 1 },
242 { "ZPUMan", 12, 3 },
259 { "WFRespFifoEmpty", 12, 1 },
294 { "MSIXParErr", 12, 3 },
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| /freebsd/sys/dev/cxgb/common/ |
| H A D | cxgb_t3_hw.c | 2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
38 * t3_wait_op_done_val - wait until an operation is completed
41 * @mask: a single-bit field within @reg that indicates completion
47 * Wait until an operation is completed by checking a bit in a register
50 * operation completes and -EAGAIN otherwise.
63 if (--attempts == 0) in t3_wait_op_done_val()
64 return -EAGAIN; in t3_wait_op_done_val()
71 * t3_write_regs - write a bunch of registers
84 while (n--) { in t3_write_regs()
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| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 * a 3-port store-and-forward switch connected to two independent
252 { -1, 0 }
331 if ((_sc)->debug) { \
341 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
342 mtx_lock(&(sc)->tx.lock); \
345 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
346 #define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
349 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \
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