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/linux/Documentation/hwmon/
H A Ducd9000.rst31 sequences up to 12 independent voltage rails. The device integrates a 12-bit
32 ADC with a 2.5V internal reference for monitoring up to 13 power supply voltage,
35 The UCD90124 is a 12-rail PMBus/I2C addressable power-supply sequencer and
36 system-health monitor. The device integrates a 12-bit ADC for monitoring up to
43 The UCD90160 is a 16-rail PMBus/I2C addressable power-supply sequencer and
44 monitor. The device integrates a 12-bit ADC for monitoring up to 16 power-supply
50 The UCD90320 is a 32-rail PMBus/I2C addressable power-supply sequencer and
56 The UCD9090 is a 10-rail PMBus/I2C addressable power-supply sequencer and
57 monitor. The device integrates a 12-bit ADC for monitoring up to 10 power-supply
63 The UCD90910 is a ten-rail I2C / PMBus addressable power-supply sequencer and
[all …]
H A Dltc4245.rst22 The LTC4245 controller allows a board to be safely inserted and removed
23 from a live backplane in multiple supply systems such as CompactPCI and
52 in1_input 12v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
65 curr4_input Vee (-12v) current (mA)
67 curr1_max_alarm 12v overcurrent alarm
70 curr4_max_alarm Vee (-12v) overcurrent alarm
[all …]
H A Dzl6100.rst110 https://flexpowermodules.com/resources/fpm-techspec-bmr450-digital-pol-regulators-20a
153 The driver is a client driver to the core PMBus driver. Please see
168 any of the i2ctools commands on a command register used to save and restore
173 and/or Flash corruption. Worst case, your board may turn into a brick.
188 Renesas/Intersil/Zilker Labs DC-DC controllers require a minimum interval
192 the driver provides a writeable module parameter, 'delay', which can be used
193 to set the interval to a value between 0 and 65,535 microseconds.
226 inX_label "vout[12]"
241 currY_label "iout[12]"
250 temp[12]_input Measured temperature.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-statistics3 KernelVersion: 2.6.12
11 KernelVersion: 2.6.12
19 KernelVersion: 2.6.12
28 KernelVersion: 2.6.12
37 KernelVersion: 2.6.12
40 Indicates the number of packets received with a CRC (FCS) error
46 KernelVersion: 2.6.12
56 KernelVersion: 2.6.12
64 KernelVersion: 2.6.12
73 KernelVersion: 2.6.12
[all …]
/linux/tools/perf/arch/x86/tests/
H A Dinsn-x86-dat-32.c13 "62 81 78 56 34 12 \tbound %eax,0x12345678(%ecx)",},
15 "62 88 78 56 34 12 \tbound %ecx,0x12345678(%eax)",},
17 "62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",},
19 "62 98 78 56 34 12 \tbound %ebx,0x12345678(%eax)",},
21 "62 a0 78 56 34 12 \tbound %esp,0x12345678(%eax)",},
23 "62 a8 78 56 34 12 \tbound %ebp,0x12345678(%eax)",},
25 "62 b0 78 56 34 12 \tbound %esi,0x12345678(%eax)",},
27 "62 b8 78 56 34 12 \tbound %edi,0x12345678(%eax)",},
31 "62 05 78 56 34 12 \tbound %eax,0x12345678",},
35 "62 14 05 78 56 34 12 \tbound %edx,0x12345678(,%eax,1)",},
[all …]
H A Dinsn-x86-dat-64.c15 "48 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%rcx",},
17 "66 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%cx",},
21 "48 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%rcx",},
23 "66 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%cx",},
25 "0f 90 80 78 56 34 12 \tseto 0x12345678(%rax)",},
27 "0f 91 80 78 56 34 12 \tsetno 0x12345678(%rax)",},
29 "0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",},
31 "0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",},
33 "0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",},
35 "0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",},
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-goramo-multilink.dts5 * - MultiLink Basic (a box)
10 * (HSS) link for a V.35 WAN interface.
45 * 74HC4094 which is used as a rudimentary GPIO expander
48 * - Write a pure DT GPIO driver using these bindings
90 * The IDSELs are 11, 12, 13, 14.
95 /* IDSEL 11 - Ethernet A */
96 <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
100 /* IDSEL 12 - Ethernet B */
101 <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
102 <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
[all …]
/linux/arch/mips/crypto/
H A Dchacha-core.S4 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
40 /* NONCE[0] is kept in a register and not in memory.
84 x(12); \
93 x(12); \
118 #define PLUS_ONE_11 12
124 #define _CONCAT3(a,b,c) a ## b ## c argument
125 #define CONCAT3(a,b,c) _CONCAT3(a,b,c) argument
129 .if (x != 12); \
134 .if (x == 12); \
146 .if (x != 12); \
[all …]
/linux/lib/crypto/
H A Dblake2s-generic.c3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
28 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
[all …]
/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
19 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
24 * THe format described in this file is deprecated. Once a reasonable
34 * struct prcm_config - define clock rates on a per-OPP basis (24xx)
36 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
40 * This is deprecated. As soon as we have a decent OPP API, we should
54 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
[all …]
/linux/arch/arm/crypto/
H A Dblake2s-core.S24 .macro __ldrd a, b, src, offset
26 ldrd \a, \b, [\src, #\offset]
28 ldr \a, [\src, #\offset]
33 .macro __strd a, b, dst, offset
35 strd \a, \b, [\dst, #\offset]
37 str \a, [\dst, #\offset]
42 .macro _le32_bswap a, tmp
44 rev_l \a, \tmp
48 .macro _le32_bswap_8x a, b, c, d, e, f, g, h, tmp
49 _le32_bswap \a, \tmp
[all …]
/linux/crypto/
H A Dblake2b_generic.c25 static const u8 blake2b_sigma[12][16] = {
26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
32 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
33 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
34 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h17 * a) "x" is the first major revision where the new field appears.
48 * DF2 N/A
124 * DF3 N/A
125 * DF3p5 N/A
126 * DF4 N/A
127 * DF4p5 N/A
161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip28-berr.c69 * Starting with a bus-address, save secondary cache (indexed by in save_cache_tags()
75 tag[0].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ in save_cache_tags()
78 tag[1].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ in save_cache_tags()
86 * than relying on VA[13:12] from the secondary cache tags to pick in save_cache_tags()
89 addr &= (0xffL << 56) | ((1 << 12) - 1); in save_cache_tags()
91 for (i = 0; i < 4; ++i, addr += (1 << 12)) { in save_cache_tags()
93 tag[0].lo = read_c0_taglo(); /* PA[35:12] */ in save_cache_tags()
96 tag[1].lo = read_c0_taglo(); /* PA[35:12] */ in save_cache_tags()
105 addr &= (0xffL << 56) | ((1 << 12) - 1); in save_cache_tags()
107 for (i = 0; i < 4; ++i, addr += (1 << 12)) { in save_cache_tags()
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dpinctrl-sg2000.h14 ((((row) - 'A' + 1) << 8) + ((col) - 1))
16 #define PIN_MIPI_TXM4 PINPOS('A', 2)
17 #define PIN_MIPIRX0N PINPOS('A', 4)
18 #define PIN_MIPIRX3P PINPOS('A', 6)
19 #define PIN_MIPIRX4P PINPOS('A', 7)
20 #define PIN_VIVO_D2 PINPOS('A', 9)
21 #define PIN_VIVO_D3 PINPOS('A', 10)
22 #define PIN_VIVO_D10 PINPOS('A', 12)
23 #define PIN_USB_VBUS_DET PINPOS('A', 13)
35 #define PIN_VIVO_D9 PINPOS('B', 12)
[all …]
H A Dpinctrl-cv1812h.h14 ((((row) - 'A' + 1) << 8) + ((col) - 1))
16 #define PIN_MIPI_TXM4 PINPOS('A', 2)
17 #define PIN_MIPIRX0N PINPOS('A', 4)
18 #define PIN_MIPIRX3P PINPOS('A', 6)
19 #define PIN_MIPIRX4P PINPOS('A', 7)
20 #define PIN_VIVO_D2 PINPOS('A', 9)
21 #define PIN_VIVO_D3 PINPOS('A', 10)
22 #define PIN_VIVO_D10 PINPOS('A', 12)
23 #define PIN_USB_VBUS_DET PINPOS('A', 13)
35 #define PIN_VIVO_D9 PINPOS('B', 12)
[all …]
/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S18 # a += m
19 # a = (r + a) % p
20 # a += s
40 # Each word in a vector consists a member of a "r/s" in [a * r/s].
223 vmulouw 12, 7, 1
230 vaddudm 14, 14, 12
234 vmulouw 12, 7, 2
236 vaddudm 15, 15, 12
243 vmulouw 12, 7, 3
245 vaddudm 16, 16, 12
[all …]
/linux/include/drm/
H A Ddrm_fixed.h4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ argument
38 #define dfixed_const_half(A) (u32)(((A) << 12) + 2048) argument
39 #define dfixed_const_666(A) (u32)(((A) << 12) + 2731) argument
40 #define dfixed_const_8(A) (u32)(((A) << 12) + 3277) argument
41 #define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) argument
42 #define dfixed_init(A) { .full = dfixed_const((A)) } argument
43 #define dfixed_init_half(A) { .full = dfixed_const_half((A)) } argument
44 #define dfixed_trunc(A) ((A).full >> 12) argument
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtda1997x.txt10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
18 - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
22 for a variety of connection possibilities including swapping pin order within
24 pairs which map a chip-specific VP output register to a 4-bit pin group. If
58 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
80 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dsc/
H A Drc_calc_fpu.c4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42 static int median3(int a, int b, int c) in median3() argument
44 if (a > b) in median3()
45 swap(a, b); in median3()
48 if (a > b) in median3()
80 TABLE_CASE(444, 12, max); in get_qp_set()
81 TABLE_CASE(444, 12, min); in get_qp_set()
86 TABLE_CASE(422, 12, max); in get_qp_set()
87 TABLE_CASE(422, 12, min); in get_qp_set()
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
42 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
45 MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
46 MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
67 MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
68 MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
69 MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
70 MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
71 MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
72 MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
[all …]
/linux/arch/riscv/include/asm/
H A Dinsn.h11 #define RV_INSN_FUNCT3_MASK GENMASK(14, 12)
12 #define RV_INSN_FUNCT3_OPOFF 12
23 #define RV_I_IMM_SIGN_OFF 12
31 #define RV_J_IMM_19_12_OPOFF 12
35 #define RV_J_IMM_19_12_OFF 12
47 #define RV_U_IMM_31_12_MASK GENMASK(31, 12)
54 #define RV_B_IMM_SIGN_OFF 12
70 #define RVC_J_IMM_SIGN_OPOFF 12
95 #define RVC_B_IMM_SIGN_OPOFF 12
110 #define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
[all …]
/linux/Documentation/networking/
H A Dnet_failover.rst11 to create and destroy a failover master netdev and manages a primary and
15 The failover netdev acts a master device and controls 2 slave devices. The
17 a passthru/vf device with the same MAC gets registered as 'primary' slave
24 datapath. It also enables hypervisor controlled live migration of a VM with
32 enabled VMs in a transparent manner with no/minimal guest userspace changes.
42 <mac address='52:54:00:00:12:53'/>
52 <mac address='52:54:00:00:12:53'/>
69 periodically be unplugged. A second attribute - 'persistent' is provided and
72 Booting a VM with the above configuration will result in the following 3
77 link/ether 52:54:00:00:12:53 brd ff:ff:ff:ff:ff:ff
[all …]
/linux/tools/testing/selftests/powerpc/math/
H A Dvsx_preempt.c7 * uses many threads and a long wait. As such, a successful test
8 * doesn't mean much but a failure is bad.
37 {1, 2, 3, 4 }, {5, 6, 7, 8 }, {9, 10,11,12},
48 long vsx_memcmp(vector int *a) { in vsx_memcmp() argument
52 FAIL_IF(a != varray); in vsx_memcmp()
54 for(i = 0; i < 12; i++) { in vsx_memcmp()
55 if (memcmp(&a[i + 12], &zero, sizeof(vector int)) == 0) { in vsx_memcmp()
56 fprintf(stderr, "Detected zero from the VSX reg %d\n", i + 12); in vsx_memcmp()
61 if (memcmp(a, &a[12], 12 * sizeof(vector int))) { in vsx_memcmp()
62 long *p = (long *)a; in vsx_memcmp()
[all …]
/linux/drivers/net/can/dev/
H A Dlength.c11 8, 12, 16, 20, 24, 32, 48, 64
23 9, 9, 9, 9, /* 9 - 12 */
26 12, 12, 12, 12, /* 21 - 24 */
49 * of a given skb.
50 * @skb: socket buffer of a CAN message.
52 * Do a rough calculation: bit stuffing is ignored and length in bits
53 * is rounded up to a length in bytes.
56 * (netdev_sent_queue() and netdev_completed_queue()) which expect a
62 * Remarks: The payload of CAN FD frames with BRS flag are sent at a

12345678910>>...53