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/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
H A Drockchip-dwmac.yaml88 For RGMII, it must be "input", means main clock(125MHz)
90 For RMII, "input" means PHY provides the reference clock(50MHz),
/linux/drivers/media/dvb-frontends/
H A Ddvb-pll.c74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
H A Dstv0367.c67 u8 bw; /* channel width 6, 7 or 8 in MHz */
268 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n"); in stv0367_pll_setup()
278 /* set internal freq to 53.125MHz */ in stv0367_pll_setup()
289 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n"); in stv0367_pll_setup()
782 wd = stv0367ter_duration(mode, 125, 500, 250); in stv0367ter_lock_algo()
835 wd = stv0367ter_duration(mode, 125, 500, 250); in stv0367ter_lock_algo()
1064 /*set IIR filter once for 6,7 or 8MHz BW*/ in stv0367ter_algo()
1428 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); in stv0367ter_snr_readreg()
1668 .frequency_min_hz = 47 * MHz,
1669 .frequency_max_hz = 862 * MHz,
[all …]
/linux/drivers/media/firewire/
H A Dfiredtv-fe.c173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
175 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
195 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h293 /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
296 823437500, /* 823.4375 MHz PLL */
301 /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
304 783360000, /* 783.36 MHz */
309 /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
312 796875000, /* 796.875 MHz */
317 /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
320 816000000, /* 816 MHz */
325 /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
328 830078125, /* 830.78125 MHz */
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
H A Dallwinner,sun7i-a20-gmac-clk.yaml26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
H A Dstarfive,jh7110-stgcrg.yaml21 - description: Main Oscillator (24 MHz)
24 - description: USB (125 MHz)
/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
39 * The external 125 MHz reference is optional, i.e. GMAC can use its
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c36 * cycle of the 125MHz RGMII TX clock):
359 /* Configure the 125MHz RGMII TX clock, the IP block changes in meson8b_init_prg_eth()
361 * a register) based on the line-speed (125MHz for Gbit speeds, in meson8b_init_prg_eth()
362 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). in meson8b_init_prg_eth()
364 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); in meson8b_init_prg_eth()
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
48 {cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,},
52 /* frequency 5200MHz */
[all …]
/linux/drivers/clk/mvebu/
H A Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/linux/arch/arm/mach-omap2/
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
113 den = 125; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
H A Domap_hwmod_81xx_data.c101 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
125 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
137 * table 1-73 for devices using 250MHz SYSCLK5 clock.
146 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
153 /* L3 med -> L4 fast peripheral interface running at 250MHz */
181 /* L3 med peripheral interface running at 200MHz */
208 /* L3 med peripheral interface running at 250MHz */
/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c32 /* this driver expects a 24MHz input frequency from the oscillator */
158 * PLL0 frequency should be multiple of 125MHz (USB frequency).
163 .fbdiv = 125,
169 .fbdiv = 125,
181 .fbdiv = 125,
193 .fbdiv = 125,
211 .fbdiv = 125,
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
362 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
485 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
486 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
487 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
488 * 3 = 125MHz in sja1110_cfg_pad_mii_id_packing()
601 /* 1000Mbps, IDIV disabled (125 MHz) */ in sja1105_rgmii_clocking_setup()
604 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ in sja1105_rgmii_clocking_setup()
607 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */ in sja1105_rgmii_clocking_setup()
698 /* PLL1 must be enabled and output 50 Mhz. in sja1105_cgu_rmii_pll_config()
[all …]
/linux/sound/soc/codecs/
H A Dtlv320aic23.c193 * 11.2896 Mhz /128 = *88.2k /192 = 58.8k
194 * 12.0000 Mhz /125 = *96k /136 = 88.235K
195 * 12.2880 Mhz /128 = *96k /192 = 64k
196 * 16.9344 Mhz /128 = 132.3k /192 = *88.2k
197 * 18.4320 Mhz /128 = 144k /192 = *96k
202 * USB BOSR 0-250/2 = 125, 1-272/2 = 136
205 128, 125, 192, 136
/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml97 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
98 60MHz for HS operation.
103 mode. Its frequency should be 19.2MHz.
205 - description: Master/Core clock, has to be >= 125 MHz
206 for SS operation and >= 60MHz for HS operation.
H A Dqcom,snps-dwc3.yaml86 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
87 60MHz for HS operation.
92 mode. Its frequency should be 19.2MHz.
190 - description: Master/Core clock, has to be >= 125 MHz
191 for SS operation and >= 60MHz for HS operation.
H A Ddwc3-xilinx.yaml40 - description: Master/Core clock, has to be >= 125 MHz
41 for SS operation and >= 60MHz for HS operation.
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c104 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
106 * divide by 100 and 125.
109 { 100, 100 }, { 125, 125 },
/linux/drivers/pwm/
H A Dpwm-ntxec.c44 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
47 #define TIME_BASE_NS 125

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