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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dmarvell,armada-3700-periph-clock.yaml45 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
47 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
48 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
49 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
50 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
51 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
H A Dallwinner,sun7i-a20-gmac-clk.yaml26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
H A Dti,dp83822.yaml87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
105 - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
106 clock frequency is 50-MHz and in RGMII Mode the clock frequency is
107 25-MHz.
109 - 'int-ref': Internal reference clock 25-MHz.
110 - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
113 - 'free-running': Free running clock 125-MHz.
114 - 'recovered': Recovered clock is a 125-MHz recovered clock from a
H A Drockchip-dwmac.txt32 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
34 PHY provides the reference clock(50MHz), "output" means GMAC provides the
H A Drockchip-dwmac.yaml88 For RGMII, it must be "input", means main clock(125MHz)
90 For RMII, "input" means PHY provides the reference clock(50MHz),
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dksz.txt23 - microchip,synclko-125 : Set if the output SYNCLKO frequency should be set to
24 125MHz instead of 25MHz.
H A Dmicrochip,ksz.yaml47 microchip,synclko-125:
50 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
56 microchip,synclko-125.
/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
48 {cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,},
52 /* frequency 5200MHz */
[all...]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1497 *op_class = 125; in ieee80211_freq_to_channel_ext()
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
1721 case 25: /* channels 149,157; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3-xilinx.txt8 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
9 operation and >= 60MHz for HS operation
H A Dqcom,dwc3.yaml97 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
98 60MHz for HS operation.
103 mode. Its frequency should be 19.2MHz.
205 - description: Master/Core clock, has to be >= 125 MHz
206 for SS operation and >= 60MHz for HS operation.
H A Dqcom,snps-dwc3.yaml86 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
87 60MHz for HS operation.
92 mode. Its frequency should be 19.2MHz.
190 - description: Master/Core clock, has to be >= 125 MHz
191 for SS operation and >= 60MHz for HS operation.
H A Ddwc3-xilinx.yaml40 - description: Master/Core clock, has to be >= 125 MHz
41 for SS operation and >= 60MHz for HS operation.
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
70 MHz (Mega Hz). When DDR frequency is less than
75 the ODT disable frequency in MHz (Mega Hz).
101 then ODT disable frequency in MHz (Mega Hz).
128 MHz (Mega Hz). When the DDR frequency is less then
190 rockchip,phy_dll_dis_freq = <125>;
/freebsd/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018_clock.c185 * P_FEPLL125 - 125MHz
186 * P_FEPLL125DLY - 125MHz
187 * P_FEPLL200 - 200MHz
188 * "fepll500" - 500MHz
192 * P_DDRPLL - 192MHz
203 * FEPLL - 48MHz (xo) input, 4GHz output
204 * DDRPLL - 48MHz (xo) input, 5.376GHz output
336 { 46400000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 29, 125 },
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
286 3: 500 kHz (125 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
603 0: 4 MHz (1 MHz)
604 1: 2 MHz (500 kHz)
[all …]
H A Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (50
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-sr-som.dtsi93 adi,phy-output-clock = "125mhz-free-running";
108 /* GPIO16 -> AR8035 25MHz */
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt8011.dtsi90 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
95 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
100 opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */
105 opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */
222 interrupts = <AIC_IRQ 125 IRQ_TYPE_LEVEL_HIGH>,
/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
276 * result and use only the 80 MHz specific version. in verify_channel()
282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
283 * result and use only the 160 MHz specific version. in verify_channel()
289 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
290 * result and use only the 80 MHz specific version. in verify_channel()
296 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_psgmii.c158 * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms in ar40xx_hw_psgmii_single_phy_testing()
219 * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms in ar40xx_hw_psgmii_all_phy_testing()
283 * for 25MHz reference clock in ar40xx_hw_malibu_psgmii_ess_reset()
/freebsd/share/man/man4/man4.arm/
H A Dbcm283x_pwm.465 Minimum frequency is 123 kHz, maximum frequency is 125 MHz.

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