| /linux/drivers/iio/adc/ |
| H A D | ad7476.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
31 struct iio_chan_spec channel[2]; member
80 if (!st->convst_gpio) in ad7091_convst()
83 gpiod_set_value(st->convst_gpio, 0); in ad7091_convst()
85 gpiod_set_value(st->convst_gpio, 1); in ad7091_convst()
92 struct iio_dev *indio_dev = pf->indio_dev; in ad7476_trigger_handler()
98 b_sent = spi_sync(st->spi, &st->msg); in ad7476_trigger_handler()
102 iio_push_to_buffers_with_timestamp(indio_dev, st->data, in ad7476_trigger_handler()
105 iio_trigger_notify_done(indio_dev->trig); in ad7476_trigger_handler()
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| H A D | imx7d_adc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
54 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << 12)
55 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << 12)
56 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12)
57 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12)
116 u32 channel; member
147 .channel = (_idx), \
166 IMX7D_ADC_CHAN(12),
181 info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4; in imx7d_adc_feature_config()
182 info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32; in imx7d_adc_feature_config()
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| H A D | ingenic-adc.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
6 * based on drivers/mfd/jz4740-adc.c
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
54 #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
70 #define JZ_ADC_AUX_VREF_BITS 12
72 #define JZ_ADC_BATTERY_LOW_VREF_BITS 12
76 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
79 #define JZ4770_ADC_BATTERY_VREF_BITS 12
118 mutex_lock(&adc->lock); in ingenic_adc_set_adcmd()
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| H A D | mcp320x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 * ------------
15 * 12 bit converter
20 * ------------
23 * ------------
72 * struct mcp320x - Microchip SPI ADC instance
74 * @msg: SPI message to select a channel and receive a value from the ADC
81 * @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
100 const unsigned int channel, bool differential) in mcp320x_channel_to_tx_data() argument
108 (channel << 2)); in mcp320x_channel_to_tx_data()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-sr.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
38 .reset = RESET_VAL(0x0, 12, 11),
44 .status = REG_VAL(0x30, 12, 1),
49 .channel = BCM_SR_GENPLL0_125M_CLK,
51 .enable = ENABLE_VAL(0x4, 6, 0, 12),
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
61 .channel = BCM_SR_GENPLL0_250M_CLK,
[all …]
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| H A D | clk-nsp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include "clk-iproc.h"
33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
37 .aon = AON_VAL(0x0, 1, 12, 0),
43 .status = REG_VAL(0x20, 12, 1),
48 .channel = BCM_NSP_GENPLL_PHY_CLK,
50 .enable = ENABLE_VAL(0x4, 12, 6, 18),
54 .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
[all …]
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| H A D | clk-cygnus.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
58 .status = REG_VAL(0x28, 12, 1),
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
65 .enable = ENABLE_VAL(0x4, 6, 0, 12),
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
[all …]
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| H A D | clk-ns2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
33 .aon = AON_VAL(0x0, 1, 15, 12),
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
51 .enable = ENABLE_VAL(0x0, 18, 12, 0),
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
67 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
[all …]
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| /linux/drivers/comedi/drivers/ |
| H A D | cb_pcidda.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for the ComputerBoards / MeasurementComputing PCI-DDA series.
9 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
15 * Description: MeasurementComputing PCI-DDA series
16 * Devices: [Measurement Computing] PCI-DDA08/12 (pci-dda08/12),
17 * PCI-DDA04/12 (pci-dda04/12), PCI-DDA02/12 (pci-dda02/12),
18 * PCI-DDA08/16 (pci-dda08/16), PCI-DDA04/16 (pci-dda04/16),
19 * PCI-DDA02/16 (pci-dda02/16)
45 #define CB_DDA_DA_CTRL_DAC(x) ((x) << 2) /* Specify DAC channel */
[all …]
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| H A D | plx9080.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
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| H A D | pcl726.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Comedi driver for 6/12-Channel D/A Output and DIO cards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: Advantech PCL-726 & compatibles
15 * Devices: [Advantech] PCL-726 (pcl726), PCL-727 (pcl727), PCL-728 (pcl728),
16 * [ADLink] ACL-6126 (acl6126), ACL-6128 (acl6128)
19 * [0] - IO Base
20 * [1] - IRQ (ACL-6126 only)
21 * [2] - D/A output range for channel 0
22 * [3] - D/A output range for channel 1
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| /linux/drivers/hsi/controllers/ |
| H A D | omap_ssi_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
26 # define SSI_MIDLEMODE_NO (1 << 12)
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
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| /linux/drivers/net/wireless/zydas/zd1211rw/ |
| H A D | zd_rf_uw2453.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
53 RF_CHANNEL(12) = 0x77,
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| /linux/sound/soc/sof/ |
| H A D | ipc4-topology.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
14 #define SOF_IPC4_FW_PAGE_SIZE BIT(12)
15 #define SOF_IPC4_FW_PAGE(x) ((((x) + BIT(12) - 1) & ~(BIT(12)
326 u32 channel; global() member
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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| H A D | ti,ads7924.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI ADS7924 4 channels 12 bits I2C analog to digital converter
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
13 Texas Instruments ADS7924 4 channels 12 bits I2C analog to digital converter
25 vref-supply:
29 reset-gpios:
35 "#address-cells":
38 "#size-cells":
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| /linux/drivers/net/wireless/broadcom/brcm80211/include/ |
| H A D | brcmu_d11.h | 1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
33 * bit 12~13 spectral band
47 #define BRCMU_CHSPEC_D11N_BND_SHIFT 12
100 BRCMU_CHAN_SB_NONE = -1,
118 * struct brcmu_chan - stores channel formats
121 * channel info and the other way.
124 * @chnum: center channel number
[all …]
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| /linux/Documentation/fb/ |
| H A D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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| /linux/Documentation/hwmon/ |
| H A D | max34440.rst | 10 Addresses scanned: -
16 PMBus 5-Channel Power-Supply Manager and Intelligent Fan Controller
20 Addresses scanned: -
26 PMBus Power-Supply Data Logger
30 Addresses scanned: -
36 PMBus 16-Channel V/I Monitor and 12-Channel Sequencer/Marginer
40 Addresses scanned: -
46 PMBus 12-Channel Voltage Monitor & Sequencer
50 Addresses scanned: -
56 PMBus 16-Channel Voltage Monitor & Sequencer
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| /linux/drivers/media/platform/nxp/imx8-isi/ |
| H A D | imx8-isi-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
33 /* Channel Image Control Register */
89 #define CHNL_IMG_CTRL_DEINT(n) ((n) << 12)
90 #define CHNL_IMG_CTRL_DEINT_MASK GENMASK(14, 12)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
141 #define CHNL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)
143 /* Channel Interrupt Enable Register */
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| /linux/Documentation/driver-api/iio/ |
| H A D | buffers.rst | 6 * :c:func:`iio_validate_scan_mask_onehot` — Validates that exactly one channel
28 The meta information associated with a channel reading placed in a buffer is
34 * :file:`enable`, used for enabling a channel. If and only if its attribute
36 channel.
37 * :file:`index`, the scan_index of the channel.
52 For example, a driver for a 3-axis accelerometer with 12 bit resolution where
53 data is stored in two 8-bits registers as follows::
56 +---+---+---+---+---+---+---+---+
58 +---+---+---+---+---+---+---+---+
61 +---+---+---+---+---+---+---+---+
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| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac4_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2015 STMicroelectronics Ltd
13 /* Define the max channel number used for tx (also rx).
72 #define DMA_SYS_BUS_AAL BIT(12)
95 /* Following DMA defines are channel-oriented */
105 addr = addrs->dma_chan + (x * addrs->dma_chan_offset); in dma_chanx_base_addr()
140 /* DMA Tx Channel X Control register defines */
142 #define DMA_CONTROL_TSE BIT(12)
146 /* DMA Rx Channel X Control register defines */
151 /* Interrupt status per channel */
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| /linux/drivers/net/wireless/intel/iwlwifi/ |
| H A D | iwl-fh.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023-2024 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-trans.h"
28 * Keep-Warm (KW) buffer base address.
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
38 * automatically invokes keep-warm accesses when normal accesses might not
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | ti-edma.txt | 3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
5 responsible for the DMA channel handling, while the TCs are responsible to
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17 channel controller(s) on 66AK2G.
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
[all …]
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| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
34 12: UART port 1
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