Lines Matching +full:12 +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
38 .reset = RESET_VAL(0x0, 12, 11),
44 .status = REG_VAL(0x30, 12, 1),
49 .channel = BCM_SR_GENPLL0_125M_CLK,
51 .enable = ENABLE_VAL(0x4, 6, 0, 12),
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
61 .channel = BCM_SR_GENPLL0_250M_CLK,
67 .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
73 .channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
79 .channel = BCM_SR_GENPLL0_PAXC_AXI_CLK,
88 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll0_clk_init()
97 .aon = AON_VAL(0x0, 1, 13, 12),
98 .reset = RESET_VAL(0x0, 12, 11),
104 .status = REG_VAL(0x30, 12, 1),
109 .channel = BCM_SR_GENPLL2_NIC_CLK,
111 .enable = ENABLE_VAL(0x4, 6, 0, 12),
115 .channel = BCM_SR_GENPLL2_TS_500_CLK,
121 .channel = BCM_SR_GENPLL2_125_NITRO_CLK,
127 .channel = BCM_SR_GENPLL2_CHIMP_CLK,
133 .channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,
139 .channel = BCM_SR_GENPLL2_FS4_CLK,
147 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll2_clk_init()
157 .reset = RESET_VAL(0x0, 12, 11),
163 .status = REG_VAL(0x30, 12, 1),
168 .channel = BCM_SR_GENPLL3_HSLS_CLK,
170 .enable = ENABLE_VAL(0x4, 6, 0, 12),
174 .channel = BCM_SR_GENPLL3_SDIO_CLK,
186 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
192 .reset = RESET_VAL(0x0, 12, 11),
198 .status = REG_VAL(0x30, 12, 1),
203 .channel = BCM_SR_GENPLL4_CCN_CLK,
205 .enable = ENABLE_VAL(0x4, 6, 0, 12),
209 .channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,
215 .channel = BCM_SR_GENPLL4_NOC_CLK,
221 .channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,
227 .channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,
236 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll4_clk_init()
246 .reset = RESET_VAL(0x0, 12, 11),
252 .status = REG_VAL(0x30, 12, 1),
257 .channel = BCM_SR_GENPLL5_FS4_HF_CLK,
258 .enable = ENABLE_VAL(0x4, 6, 0, 12),
262 .channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,
263 .enable = ENABLE_VAL(0x4, 7, 1, 12),
267 .channel = BCM_SR_GENPLL5_RAID_AE_CLK,
275 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll5_clk_init()
288 .status = REG_VAL(0x38, 12, 1),
293 .channel = BCM_SR_LCPLL0_SATA_REFP_CLK,
299 .channel = BCM_SR_LCPLL0_SATA_REFN_CLK,
305 .channel = BCM_SR_LCPLL0_SATA_350_CLK,
311 .channel = BCM_SR_LCPLL0_SATA_500_CLK,
320 iproc_pll_clk_setup(pdev->dev.of_node, in sr_lcpll0_clk_init()
333 .status = REG_VAL(0x38, 12, 1),
338 .channel = BCM_SR_LCPLL1_WAN_CLK,
344 .channel = BCM_SR_LCPLL1_USB_REF_CLK,
350 .channel = BCM_SR_LCPLL1_CRMU_TS_CLK,
359 iproc_pll_clk_setup(pdev->dev.of_node, in sr_lcpll1_clk_init()
372 .status = REG_VAL(0x38, 12, 1),
377 .channel = BCM_SR_LCPLL_PCIE_PHY_REF_CLK,
386 iproc_pll_clk_setup(pdev->dev.of_node, in sr_lcpll_pcie_clk_init()
393 { .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
394 { .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
395 { .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
396 { .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
397 { .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
398 { .compatible = "brcm,sr-lcpll1", .data = sr_lcpll1_clk_init },
399 { .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
407 probe_func = of_device_get_match_data(&pdev->dev); in sr_clk_probe()
409 return -ENODEV; in sr_clk_probe()
416 .name = "sr-clk",