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/linux/lib/crypto/x86/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * Copyright (C) 2017-2019 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
22 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
23 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
24 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
25 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
26 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
27 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
28 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
[all …]
/linux/drivers/scsi/
H A Dmyrb.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
163 unsigned char ldev_count; /* Byte 0 */
164 unsigned int rsvd1:24; /* Bytes 1-3 */
165 unsigned int ldev_sizes[32]; /* Bytes 4-131 */
166 unsigned short flash_age; /* Bytes 132-133 */
168 unsigned char deferred:1; /* Byte 134 Bit 0 */
169 unsigned char low_bat:1; /* Byte 134 Bit 1 */
170 unsigned char rsvd2:6; /* Byte 134 Bits 2-7 */
172 unsigned char rsvd3:8; /* Byte 135 */
[all …]
H A Dmyrs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
109 } __packed mem_type:5; /* Byte 0 Bits 0-4 */
110 unsigned rsvd:1; /* Byte 0 Bit 5 */
111 unsigned mem_parity:1; /* Byte 0 Bit 6 */
112 unsigned mem_ecc:1; /* Byte 0 Bit 7 */
132 unsigned char rsvd1; /* Byte 0 */
137 } __packed bus; /* Byte 1 */
170 } __packed ctlr_type; /* Byte 2 */
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-sdr-pcu20be.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU20BE:
9 Planar complex unsigned 20-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
23 **Byte Order.**
24 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 1
28 :stub-columns: 0
30 * - Offset:
[all …]
H A Dpixfmt-packed-yuv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
30 seen in a 16-bit word, which is then stored in memory in little endian byte
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
44 .. flat-table:: Packed YUV 4:4:4 Image Formats (less than 8bpc)
45 :header-rows: 2
[all …]
/linux/drivers/scsi/isci/
H A Dsas.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
109 u8 _r_c[12];
114 * struct smp_req_phy_id - This structure defines the contents of
123 u8 _r_a[4]; /* bytes 4-7 */
125 u8 ign_zone_grp:1; /* byte 8 */
128 u8 phy_id; /* byte 9 */
129 u8 _r_c; /* byte 10 */
130 u8 _r_d; /* byte 11 */
[all …]
/linux/arch/powerpc/kernel/vdso/
H A Dsigtramp32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
42 .byte 0x0f; /* DW_CFA_def_cfa_expression */ \
43 .uleb128 9f - 1f; /* length */ \
45 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
46 .byte 0x06; /* DW_OP_deref */ \
47 .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
48 .byte 0x06; /* DW_OP_deref */ \
54 .byte 0x10; /* DW_CFA_expression */ \
56 .uleb128 9f - 1f; /* length */ \
[all …]
H A Dsigtramp64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 .quad 0,-21*8
47 .byte 0x0f; /* DW_CFA_def_cfa_expression */ \
48 .uleb128 9f - 1f; /* length */ \
50 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
51 .byte 0x06; /* DW_OP_deref */ \
52 .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
53 .byte 0x06; /* DW_OP_deref */ \
59 .byte 0x10; /* DW_CFA_expression */ \
61 .uleb128 9f - 1f; /* length */ \
[all …]
/linux/arch/xtensa/lib/
H A Dmemcopy.S2 * arch/xtensa/lib/hal/memcopy.S -- Core HAL library functions
9 * Copyright (C) 2002 - 2012 Tensilica Inc.
24 * 32-bit load and store instructions (as required for these
36 * 8, 4, 2, and 1 byte copies conditional on the length;
39 * This code tries to use fall-through branches for the common
61 * Byte by byte copy
64 .byte 0 # 1 mod 4 alignment for LOOPNEZ
89 .Ldst1mod2: # dst is only byte aligned
90 _bltui a4, 7, .Lbytecopy # do short copies byte by byte
92 # copy 1 byte
[all …]
H A Dusercopy.S8 * of the Xtensa link-time HAL, and those files may differ per
11 * could lose the special functionality for accessing user-space
37 * This code tries to use fall-through braches for the common
80 __ssa8 a3 # set shift amount from byte offset
89 .Ldst1mod2: # dst is only byte aligned
90 bltui a4, 7, .Lbytecopy # do short copies byte by byte
92 # copy 1 byte
97 addi a4, a4, -1
100 .Ldst2mod4: # dst 16-bit aligned
102 bltui a4, 6, .Lbytecopy # do short copies byte by byte
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-arm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/kernel/kprobes-test-arm.c
14 #include "test-core.h"
55 TEST_GROUP("Data-processing (register), (register-shifted register), (immediate)") in kprobe_arm_test_cases()
155 /* Data-processing with PC and a shift count in a register */ in kprobe_arm_test_cases()
167 /* Data-processing with PC as a target and status registers updated */ in kprobe_arm_test_cases()
175 /* Data-processing with SP as target */ in kprobe_arm_test_cases()
181 TEST_PRR("add sp, r",10,0,", r",11,4,", asl r",12,1,"") in kprobe_arm_test_cases()
183 TEST_PR( "mov sp, r",10,0,", asl r",12,0,"") in kprobe_arm_test_cases()
185 /* Data-processing with PC as target */ in kprobe_arm_test_cases()
[all …]
/linux/tools/testing/selftests/bpf/verifier/
H A Dctx_sk_lookup.c2 "valid 1,2,4,8-byte reads from bpf_sk_lookup",
4 /* 1-byte read from family field */
13 /* 2-byte read from family field */
18 /* 4-byte read from family field */
22 /* 1-byte read from protocol field */
31 /* 2-byte read from protocol field */
36 /* 4-byte read from protocol field */
40 /* 1-byte read from remote_ip4 field */
49 /* 2-byte read from remote_ip4 field */
54 /* 4-byte read from remote_ip4 field */
[all …]
/linux/arch/powerpc/crypto/
H A Daesp10-ppc.pl2 # SPDX-License-Identifier: GPL-2.0
12 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # The module is endian-agnostic in sense that it supports both big-
59 # and little-endian cases. Data alignment in parallelizable modes is
64 # is aligned programmatically, which in turn guarantees exception-
72 # Add XTS subroutine, 9x on little- and 12x improvement on big-endian
76 # Current large-block performance in cycles per byte processed with
77 # 128-bit key (less is better).
79 # CBC en-/decrypt CTR XTS
106 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
[all …]
/linux/lib/crypto/arm/
H A Dchacha-neon-core.S11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSE3 functions
26 * (c) vrev32.16 (16-bit rotations only)
30 * ChaCha has 16, 12, 8, and 7-bit rotations. For the 12 and 7-bit rotations,
31 * the only choices are (a) and (b). We use (a) since it takes two-thirds the
32 * cycles of (b) on both Cortex-A7 and Cortex-A53.
34 * For the 16-bit rotation, we use vrev32.16 since it's consistently fastest
37 * For the 8-bit rotation, we use vtbl.8 + vtbl.8. On Cortex-A7, this sequence
42 * A disadvantage is that on Cortex-A53, the vtbl sequence is the same speed as
46 * CPUs, e.g. ~4.8% faster ChaCha20 on Cortex-A7.
57 * chacha_permute - permute one block
[all …]
/linux/arch/x86/math-emu/
H A Dpoly.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*---------------------------------------------------------------------------+
5 | Header file for the FPU-emu poly*.c source files. |
9 | Australia. E-mail billm@melbpc.org.au |
11 | Declarations and definitions for functions operating on Xsig (12-byte |
12 | extended-significand) quantities. |
14 +---------------------------------------------------------------------------*/
19 /* This 12-byte structure is used to improve the accuracy of computation
21 Intended to be used to get results better than 8-byte computation
22 allows. 9-byte would probably be sufficient.
[all …]
/linux/include/scsi/
H A Dsas.h1 /* SPDX-License-Identifier: GPL-2.0-only */
132 SAS_PRIM_BC_R0 = 12,
179 SAS_OREJ_RSVD_CONT0 = 12,
255 /* Byte 0 */
260 /* Byte 1 */
263 /* Byte 2 */
275 /* Byte 3 */
287 /* Byte 4 - 11 */
290 /* Byte 12 - 19 */
293 /* Byte 20 */
[all …]
/linux/arch/powerpc/boot/
H A Dcrt0.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 p_start: .8byte _start
28 p_etext: .8byte _etext
29 p_bss_start: .8byte __bss_start
30 p_end: .8byte _end
32 p_toc: .8byte .TOC. - p_base
33 p_dyn: .8byte __dynamic_start - p_base
34 p_rela: .8byte __rela_dyn_start - p_base
35 p_prom: .8byte 0
37 p_pstack: .8byte _platform_stack_top
[all …]
/linux/arch/riscv/include/asm/
H A Dinsn-def.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define INSN_R_FUNC3_SHIFT 12
17 #define INSN_I_FUNC3_SHIFT 12
24 #define INSN_S_FUNC3_SHIFT 12
46 #include <asm/gpr-num.h>
49 .4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \
58 .4byte ((\opcode << INSN_I_OPCODE_SHIFT) | \
66 .4byte ((\opcode << INSN_S_OPCODE_SHIFT) | \
96 #include <asm/gpr-num.h>
101 " .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_packet.h78 /* Not an actual hardware packet -- this is what we use to put
162 * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
175 * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
181 #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP BIT(12)
192 * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
224 /** @{ byte 2 of config bits. */
229 /** @{ byte 1 of config bits. */
231 /** same values in this 3-bit field as PIPE_FUNC_* */
243 /** @{ byte 0 of config bits. */
278 #define VC4_RENDER_CONFIG_DB_NON_MS BIT(12)
[all …]
/linux/drivers/crypto/caam/
H A Dpdb.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright 2008-2016 Freescale Semiconductor, Inc.
14 * PDB- IPSec ESP Header Modification Options
19 * Encap and Decap - Decrement TTL (Hop Limit) - Based on the value of the
20 * Options Byte IP version (IPvsn) field:
21 * if IPv4, decrement the inner IP header TTL field (byte 8);
22 * if IPv6 decrement the inner IP header Hop Limit field (byte 7).
27 * Decap - DiffServ Copy - Copy the IPv4 TOS or IPv6 Traffic Class byte
32 * Encap- Copy DF bit -if an IPv4 tunnel mode outer IP header is coming from
47 * PDB - IPSec ESP Encap/Decap Options
[all …]
/linux/arch/powerpc/include/asm/
H A Drtas-types.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 /* Byte 0 */
28 /* Byte 1 */
37 /* Byte 2 */
53 /* Byte 0 */
66 /* Byte 1 */
69 /* Byte 2 */
74 * XXXX 4: Log format used for bytes 12-2047
77 /* Byte 3 */
79 /* Byte 4-11 */
[all …]
H A Dsmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * These commands are used to retrieve the sdb-partition-XX datas from
26 * the SMU. The length is always 2. First byte is the subcommand code
27 * and second byte is the partition ID.
31 * - 0..1 : partition address
32 * - 2 : a byte containing the partition ID
33 * - 3 : length (maybe other bits are rest of header ?)
48 * act differently based on the number of arguments. With 1 byte
52 * Queries (1 byte arg):
53 * ---------------------
[all …]
/linux/arch/riscv/kernel/vdso/
H A Dvgetrandom-chacha.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Based on arch/loongarch/vdso/vgetrandom-chacha.S.
14 slliw t0, \rs, 32 - \imm
28 * a1: 32-byte key input
29 * a2: 8-byte counter input/output
30 * a3: number of 64-byte blocks to write to output
79 * The ABI requires s0-s9 saved.
80 * This does not violate the stack-less requirement: no sensitive data
83 addi sp, sp, -12*SZREG
105 /* state[0,1,2,3] = "expand 32-byte k" */
[all …]
/linux/arch/x86/crypto/
H A Dcast6-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast6 Cipher 8-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
8 * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
13 #include "glue_helper-asm-avx.S"
15 .file "cast6-avx-x86_64-asm_64.S"
24 #define kr (12*4*4)
26 /* s-boxes */
33 8-way AVX cast6
186 /* add 16-bit rotation to key rotations (mod 32) */ \
[all …]
/linux/arch/x86/lib/
H A Dchecksum_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
28 #include <asm/nospec-branch.h>
44 * is aligned on either a 2-byte or 4-byte boundary. We get at
45 * least a twofold speedup on 486 and Pentium if it is 4-byte aligned.
46 * Fortunately, it is easy to convert 2-byte alignment to 4-byte
54 movl 12(%esp),%esi # Function arg: unsigned char *buff
89 movl 12(%esi), %ebx
124 testb $1, 12(%esp)
142 movl 12(%esp),%esi # Function arg: const unsigned char *buf
158 # Handle 2-byte-aligned regions
[all …]

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