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/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
24 /* from BPP 4 to 12 in steps of 0.5 */
67 { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
90 { 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
92 { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
94 { 12, 12, 12, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
96 { 12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7,
98 { 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8,
100 { 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
144 { 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11,
[all …]
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
12 # 2. c += d; b ^= c; b <<<= 12;
17 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
204 vpermxor 12, 12, 0, 25
205 vpermxor 13, 13, 1, 25
213 vadduwm 8, 8, 12
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
49 RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
50 RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
61 RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
85 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
86 RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
91 RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
92 RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
[all …]
/linux/sound/soc/codecs/
H A Drt5640.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
[all …]
H A Drt5651.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
[all …]
H A Drt5616.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5616.h -- RT5616 ALSA SoC audio driver
17 /* I/O - Output */
21 /* I/O - Input */
24 /* I/O - ADC/DAC/DMIC */
28 /* Mixer - D-D */
33 /* Mixer - ADC */
38 /* Mixer - DAC */
57 /* Format - ADC/DAC */
62 /* Function - Analog */
[all …]
H A Drt5645.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer -
[all...]
H A Drt5670.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
17 /* I/O - Output */
20 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
34 /* Mixer - D-D */
47 /* Mixer - PDM */
56 /* Mixer - ADC */
61 /* Mixer - DAC */
77 /* Format - ADC/DAC */
[all …]
H A Drt5665.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
[all …]
H A Drt5659.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
31 /* I/O - Input */
36 /* I/O - Speaker */
42 /* I/O - Sidetone */
44 /* I/O - ADC/DAC/DMIC */
56 /* Mixer - D-D */
65 /* Mixer - PDM */
73 /* Mixer - ADC */
[all …]
H A Drt1015.h1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.h -- RT1015 ALSA SoC audio amplifier driver
188 #define RT1015_PLL_SEL_MASK (0x1 << 13)
189 #define RT1015_PLL_SEL_SFT 13
190 #define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13)
191 #define RT1015_PLL_SEL_BCLK (0x1 << 13)
197 #define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12)
198 #define RT1015_PLL_M_SFT 12
233 #define RT1015_DAC_CLK (0x1 << 13)
234 #define RT1015_DAC_CLK_BIT 13
[all …]
H A Drt5631.h1 /* SPDX-License-Identifier: GPL-2.0 */
115 #define RT5631_MUTE_MONO (0x1 << 13)
116 #define RT5631_MUTE_MONO_SHIFT 13
135 #define RT5631_M_AXIL_TO_RECMIXER_L (0x1 << 13)
136 #define RT5631_M_AXIL_RECMIXL_BIT 13
137 #define RT5631_M_MONO_IN_TO_RECMIXER_L (0x1 << 12)
138 #define RT5631_M_MONO_IN_RECMIXL_BIT 12
153 #define RT5631_M_DAC_L_TO_OUTMIXER_L (0x1 << 13)
154 #define RT5631_M_DACL_OUTMIXL_BIT 13
155 #define RT5631_M_MIC1_TO_OUTMIXER_L (0x1 << 12)
[all …]
H A Drt5660.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5660.h -- RT5660 ALSA SoC audio driver
20 /* I/O - Output */
23 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
30 /* Mixer - D-D */
35 /* Mixer - ADC */
40 /* Mixer - DAC */
61 /* Format - ADC/DAC */
66 /* Function - Analog */
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2712.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt2712.h"
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
46 MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
56 MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
[all …]
H A Dpinctrl-mt8196.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-mtk-mt8196.h"
11 #include "pinctrl-paris.h"
47 PIN_FIELD_BASE(9, 9, 9, 0x0120, 0x10, 13, 1),
48 PIN_FIELD_BASE(10, 10, 9, 0x0120, 0x10, 12, 1),
50 PIN_FIELD_BASE(12, 12, 9, 0x0120, 0x10, 15, 1),
51 PIN_FIELD_BASE(13, 13, 6, 0x0120, 0x10, 3, 1),
129 PIN_FIELD_BASE(91, 91, 12, 0x00c0, 0x10, 5, 1),
130 PIN_FIELD_BASE(92, 92, 12, 0x00c0, 0x10, 5, 1),
131 PIN_FIELD_BASE(93, 93, 12, 0x00c0, 0x10, 5, 1),
[all …]
/linux/lib/crypto/arm64/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
17 * assemblers both consider the SHA-512 instructions to be part of the
20 * versions.) "sha3" doesn't make a lot of sense, since SHA-512 is part
21 * of the SHA-2 family of algorithms, and also the Arm Architecture
25 .arch armv8-a+sha3
28 * The SHA-512 round constants
102 ld1 {v8.2d-v11.2d}, [x0]
106 ld1 {v20.2d-v23.2d}, [x3], #64
109 0: ld1 {v12.2d-v15.2d}, [x1], #64
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32mp135.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH1_MII_CRS"),
23 STM32_FUNCTION(13, "ETH2_MII_CRS"),
35 STM32_FUNCTION(12, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
46 STM32_FUNCTION(12, "ETH1_MDIO"),
59 STM32_FUNCTION(12, "ETH1_MII_COL"),
60 STM32_FUNCTION(13, "ETH2_MII_COL"),
72 STM32_FUNCTION(12, "ETH2_PPS_OUT"),
[all …]
H A Dpinctrl-stm32h743.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
24 STM32_FUNCTION(12, "ETH_MII_CRS"),
39 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
53 STM32_FUNCTION(12, "ETH_MDIO"),
54 STM32_FUNCTION(13, "MDIOS_MDIO"),
69 STM32_FUNCTION(12, "ETH_MII_COL"),
82 STM32_FUNCTION(13, "OTG_HS_SOF"),
110 STM32_FUNCTION(12, "MDIOS_MDC"),
111 STM32_FUNCTION(13, "TIM1_BKIN_COMP12"),
[all …]
/linux/lib/crypto/
H A Dchacha-block-generic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 u32 *x = state->x; in chacha_permute()
22 WARN_ON_ONCE(nrounds != 20 && nrounds != 12); in chacha_permute()
25 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
26 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
30 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
31 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
32 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
33 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
35 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
[all …]
/linux/include/linux/mfd/wm831x/
H A Dregulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
14 * R16462 (0x404E) - Current Sink 1
26 #define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
29 #define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */
30 #define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
32 #define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */
33 #define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */
[all …]
H A Dauxadc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x
16 * R16429 (0x402D) - AuxADC Data
18 #define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
19 #define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */
20 #define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */
21 #define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
22 #define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
23 #define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
26 * R16430 (0x402E) - AuxADC Control
[all …]
/linux/lib/crypto/x86/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * Copyright (C) 2017-2019 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
22 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
23 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
24 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
25 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
26 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
27 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
28 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
205 BUS_MSTOP(10, BIT(12))),
215 BUS_MSTOP(2, BIT(13))),
219 BUS_MSTOP(11, BIT(13))),
225 BUS_MSTOP(12, BIT(0))),
228 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
230 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
[all …]
/linux/lib/crypto/mips/
H A Dchacha-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2016-2018 René van Dorst <opensource@vdorst.com>. All Rights Reserved.
4 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
80 x(12); \
81 x(13); \
88 x(13); \
89 x(12); \
114 #define PLUS_ONE_11 12
115 #define PLUS_ONE_12 13
125 .if (x != 12); \
[all …]

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