Lines Matching +full:12 +full:- +full:13
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
205 BUS_MSTOP(10, BIT(12))),
215 BUS_MSTOP(2, BIT(13))),
219 BUS_MSTOP(11, BIT(13))),
225 BUS_MSTOP(12, BIT(0))),
228 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
230 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
235 BUS_MSTOP(5, BIT(12))),
237 BUS_MSTOP(5, BIT(12))),
239 BUS_MSTOP(5, BIT(13))),
241 BUS_MSTOP(5, BIT(13))),
258 DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
269 BUS_MSTOP(3, BIT(13))),
310 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
312 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
334 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
336 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
342 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
344 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
346 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
348 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
350 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
352 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
354 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
356 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
358 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
360 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
362 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
364 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
366 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
368 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
370 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
372 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
392 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
404 DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
405 DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
406 DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
416 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
417 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
418 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
427 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
428 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
433 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
434 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
435 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
436 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
437 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
438 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
439 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
440 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
441 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
442 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
443 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
444 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
445 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
446 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
447 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */