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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-ls2080a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "fsl-ls2080a.dtsi"
16 #include "fsl-ls208xa-rdb.dtsi"
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
24 stdout-path = "serial1:115200n8";
29 phy-handle = <&mdio2_phy1>;
30 phy-connection-type = "10gbase-r";
34 phy-handle = <&mdio2_phy2>;
[all …]
H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
[all …]
H A Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2019-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
27 stdout-path = "serial0:115200n8";
40 mmc-hs200-1_8v;
41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
[all …]
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux-0 {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
23 i2c0_emux: i2c-mux-1 {
[all …]
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_devids.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
9 /* Intel(R) Ethernet Connection E823-L for backplane */
11 /* Intel(R) Ethernet Connection E823-L for SFP */
13 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
15 /* Intel(R) Ethernet Connection E823-L 1GbE */
17 /* Intel(R) Ethernet Connection E823-L for QSFP */
19 /* Intel(R) Ethernet Controller E830-CC for backplane */
21 /* Intel(R) Ethernet Controller E830-CC for QSFP */
23 /* Intel(R) Ethernet Controller E830-CC for SFP */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
H A Dmediatek,mt7988-xfi-tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7988 XFI T-PHY
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
15 MediaTek's 10G-capabale MT7988 SoC.
20 const: mediatek,mt7988-xfi-tphy
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
H A Darmada-8040-mcbin-singleshot.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/leds/common.h>
10 #include "armada-8040-mcbin.dtsi"
13 model = "Marvell 8040 MACCHIATOBin Single-shot";
14 compatible = "marvell,armada8040-mcbin-singleshot",
15 "marvell,armada8040-mcbin", "marvell,armada8040",
16 "marvell,armada-ap806-quad", "marvell,armada-ap806";
19 compatible = "gpio-leds";
20 pinctrl-0 = <&cp0_led18_pins>;
21 pinctrl-names = "default";
[all …]
H A Dcn9130-crb.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
29 ap0_reg_mmc_vccq: regulator-1 {
30 compatible = "regulator-gpio";
31 regulator-name = "ap0_mmc_vccq";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3300000>;
39 cp0_reg_usb3_vbus1: regulator-2 {
40 compatible = "regulator-fixed";
[all …]
H A Dcn9132-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9132-sr-cex7.dtsi"
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
32 gpio-keys {
33 compatible = "gpio-keys";
[all …]
H A Dcn9130-cf.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
19 reg_usb3_vbus0: regulator-usb3-vbus0 {
20 compatible = "regulator-fixed";
21 regulator-name = "vbus0";
22 regulator-min-microvolt = <5000000>;
23 regulator-max-microvolt = <5000000>;
29 i2c-bus = <&cp0_i2c1>;
30 los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
31 mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
[all …]
H A Dcn9130-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9130-DB board.
10 #include <dt-bindings/gpio/gpio.h>
14 stdout-path = "serial0:115200n8";
33 ap0_reg_sd_vccq: regulator-1 {
34 compatible = "regulator-gpio";
35 regulator-name = "ap0_sd_vccq";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <3300000>;
42 cp0_reg_usb3_vbus0: regulator-2 {
[all …]
/linux/Documentation/networking/
H A Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
144 * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/linux/drivers/net/phy/
H A Dqt2025.rs1 // SPDX-License-Identifier: GPL-2.0
8 //! and firmware can be downloaded on the EN-9320SFP+ support site.
10 //! The QT2025 PHY integrates an Intel 8051 micro-controller.
32 firmware: ["qt2025-2.0.3.3.fw"],
39 const NAME: &'static CStr = c_str!("QT2025 10Gpbs SFP+");
42 fn probe(dev: &mut phy::Device) -> Result<()> { in probe()
50 // `MICRO_RESETN`: hold the micro-controller in reset while configuring. in probe()
52 // `SREFCLK_FREQ`: configure clock frequency of the micro-controller. in probe()
59 // 3.41 5/10/25GBASE-R PCS test pattern seed B) for something else. in probe()
67 // `MICRO_RESETN`: release the micro-controller from the reset state. in probe()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
44 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10)
59 #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10)
72 #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10)
83 #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10)
[all...]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c2 * AMD 10Gb Ethernet driver
125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
158 #define XGBE_RRC_FREQUENCY 10
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
375 /* Re-driver support */
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
34 /* [R 1] ATC initialization done */
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
128 for (compat = xpcs->desc->compat; compat->supported; compat++) in xpcs_find_compat()
129 if (compat->interface == interface) in xpcs_find_compat()
137 return &xpcs->pcs; in xpcs_to_phylink_pcs()
147 return -ENODEV; in xpcs_get_an_mode()
149 return compat->an_mode; in xpcs_get_an_mode()
158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
159 if (compat->supported[i] == linkmode) in __xpcs_linkmode_supported()
[all …]

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