| /linux/drivers/iio/adc/ |
| H A D | max1363.c | 132 * @bits: accuracy of the adc in bits
142 u8 bits; member
251 MAX1363_MODE_SINGLE(10, 1 << 10),
259 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
265 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
281 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
282 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
291 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
392 if (st->chip_info->bits != 8) { in max1363_read_single_chan()
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-yuv-planar.rst | 50 All components are stored with the same number of bits per component.
64 - Bits per component
115 - 10
122 - 10
143 - 10
161 - 16x32 / 16x16 tiles tiled low bits
168 - 16x32 / 16x16 tiles raster low bits
199 - 10
258 - Y'\ :sub:`10`
278 - Cb\ :sub:`10`
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| H A D | pixfmt-srggb10p.rst | 17 10-bit packed Bayer formats
23 These four pixel formats are packed raw sRGB / Bayer formats with 10
24 bits per sample. Every four consecutive samples are packed into 5
25 bytes. Each of the first 4 bytes contain the 8 high order bits
27 bits of each pixel, in the same order.
49 - G\ :sub:`03low`\ (bits 7--6) B\ :sub:`02low`\ (bits 5--4)
51 G\ :sub:`01low`\ (bits 3--2) B\ :sub:`00low`\ (bits 1--0)
53 - G\ :sub:`10high`
57 - R\ :sub:`13low`\ (bits 7--6) G\ :sub:`12low`\ (bits 5--4)
59 R\ :sub:`11low`\ (bits 3--2) G\ :sub:`10low`\ (bits 1--0)
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| /linux/arch/arm/mach-omap2/ |
| H A D | prcm-common.h | 66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
91 #define OMAP24XX_EN_GPT8_SHIFT 10
92 #define OMAP24XX_EN_GPT8_MASK (1 << 10)
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
109 #define OMAP2430_EN_GPIO5_SHIFT 10
110 #define OMAP2430_EN_GPIO5_MASK (1 << 10)
122 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
130 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
153 #define OMAP24XX_ST_GPT8_SHIFT 10
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| /linux/arch/arc/include/asm/ |
| H A D | disasm.h | 32 #define BITS(word, s, e) (((word) >> (s)) & (~((-2) << ((e) - (s))))) macro
34 #define MAJOR_OPCODE(word) (BITS((word), 27, 31))
35 #define MINOR_OPCODE(word) (BITS((word), 16, 21))
36 #define FIELD_A(word) (BITS((word), 0, 5))
37 #define FIELD_B(word) ((BITS((word), 12, 14)<<3) | \
38 (BITS((word), 24, 26)))
39 #define FIELD_C(word) (BITS((word), 6, 11))
41 #define FIELD_s12(word) sign_extend(((BITS((word), 0, 5) << 6) | \
42 BITS((word), 6, 11)), 12)
46 #define FIELD_s9(word) sign_extend(((BITS(word, 15, 15) << 8) | \
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| /linux/include/uapi/linux/usb/ |
| H A D | ch11.h | 17 * have up to 255 ports. The most yet reported is 10.
24 /* See USB 3.1 spec Table 10-5 */
36 * See USB 3.1 spec Table 10-12
48 #define HUB_GET_TT_STATE 10
53 * See USB 3.0 spec Table 10-6
88 * See USB 3.0 spec Table 10-7
102 /* USB 3.0 hub remote wake mask bits, see table 10-14 */
105 #define USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT (1 << 10)
111 * See USB 3.1 spec section 10.16.2.6 Table 10-12 and 10-15
129 /* bits 6 to 7 are reserved */
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| /linux/drivers/media/radio/si470x/ |
| H A D | radio-si470x.h | 41 #define DEVICEID_PN 0xf000 /* bits 15..12: Part Number */
42 #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
45 #define SI_CHIPID_REV 0xfc00 /* bits 15..10: Chip Version */
46 #define SI_CHIPID_DEV 0x0200 /* bits 09..09: Device */
47 #define SI_CHIPID_FIRMWARE 0x01ff /* bits 08..00: Firmware Version */
50 #define POWERCFG_DSMUTE 0x8000 /* bits 15..15: Softmute Disable */
51 #define POWERCFG_DMUTE 0x4000 /* bits 14..14: Mute Disable */
52 #define POWERCFG_MONO 0x2000 /* bits 13..13: Mono Select */
53 #define POWERCFG_RDSM 0x0800 /* bits 11..11: RDS Mode (Si4701 only) */
54 #define POWERCFG_SKMODE 0x0400 /* bits 10..10: Seek Mode */
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| /linux/drivers/cpufreq/ |
| H A D | powernow-k7.c | 41 u8 signature[10];
64 } bits; member
77 /* divide by 10 to get FID. */
185 powernow_table[j].frequency = (fsb * fid_codes[fid]) / 10; in get_ranges()
186 powernow_table[j].driver_data = fid; /* lower 8 bits */ in get_ranges()
190 if ((fid_codes[fid] % 10) == 5) { in get_ranges()
203 powernow_table[j].driver_data |= (vid << 8); /* upper 8 bits */ in get_ranges()
206 "VID: 0x%x (%d.%03dV)\n", fid, fid_codes[fid] / 10, in get_ranges()
207 fid_codes[fid] % 10, speed/1000, vid, in get_ranges()
223 if (fidvidctl.bits.FID != fid) { in change_FID()
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| /linux/include/uapi/drm/ |
| H A D | drm_fourcc.h | 143 /* 10 bpp Red (direct relationship between channel value and brightness) */
144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
203 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little …
204 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little …
205 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little …
206 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little …
208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | regs-mixer.h | 65 /* generates mask for range of bits */
72 /* bits for MXR_STATUS */
82 /* bits for MXR_CFG */
87 #define MXR_CFG_RGB601 (0 << 10)
88 #define MXR_CFG_RGB709 (1 << 10)
110 /* bits for MXR_VIDEO_CFG */
113 /* bits for MXR_GRAPHICn_CFG */
123 /* bits for MXR_GRAPHICn_WH */
127 #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)
129 /* bits for MXR_RESOLUTION */
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| /linux/arch/x86/math-emu/ |
| H A D | README | 74 a value of pi which is accurate to more than 128 bits. As a consequence,
75 the reduced argument is accurate to more than 64 bits for arguments up
76 to a few pi, and accurate to more than 64 bits for most arguments,
78 80486, which uses a value of pi which is accurate to 66 bits.
240 would be 64 bits. The reduced Turbo C accuracy of cos() and tan() for
242 precision of the argument x; e.g. an argument of pi/2-(1e-10) which is
243 accurate to 64 bits can result in a relative accuracy in cos() of
244 about 64 + log2(cos(x)) = 31 bits.
248 (relative bits)
251 atan(x) 1e-10 .. 200 64.2 62.8
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| /linux/drivers/net/ipa/reg/ |
| H A D | ipa_reg-v5.5.c | 6 #include <linux/bits.h>
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
62 [HPS_DPS_CMDQS] = BIT(10),
95 /* Bits 29-31 reserved */
110 /* Bits 8-31 reserved */
118 /* Bits 8-15 reserved */
125 /* Valid bits defined by ipa->available */
131 /* Bits 1-3 reserved */
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| H A D | ipa_reg-v4.2.c | 6 #include <linux/bits.h>
23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
31 /* Bits 21-31 reserved */
47 [HPS_DPS_CMDQS] = BIT(10),
67 /* Bits 30-31 reserved */
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
95 /* Bits 8-31 reserved */
103 /* Bits 8-15 reserved */
112 /* Bits 1-3 reserved */
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| H A D | ipa_reg-v5.0.c | 6 #include <linux/bits.h>
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
45 /* Bits 28-29 reserved */
63 [HPS_DPS_CMDQS] = BIT(10),
96 /* Bits 29-31 reserved */
111 /* Bits 8-31 reserved */
119 /* Bits 8-15 reserved */
126 /* Valid bits defined by ipa->available */
132 /* Bits 1-3 reserved */
134 /* Bits 5-31 reserved */
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| /linux/drivers/net/ethernet/dec/tulip/ |
| H A D | pnic2.c | 18 * As I understand things, here are the registers and bits that
23 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
30 * Bit 11:10 - Loop Back Operation Mode
31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
35 * CSR 14 (mask = 0xfff0ee39 of bits not to change)
43 * Bit 6 - HDE - Advertise 10baseT-HD
45 * Bit 1 - Loop Back enable for 10baseT MCC
53 * Bit 22 - Partner can do 10baseT-FD
54 * Bit 21 - Partner can do 10baseT-HD
55 * Bit 15 - LPN is 1 if all above bits are valid other wise 0
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| /linux/drivers/ras/amd/atl/ |
| H A D | reg_fields.h | 28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
94 * Rev Fieldname Bits
119 * Rev Fieldname Bits
137 * Rev Fieldname Bits
158 * Rev Fieldname Bits
180 * Rev Fieldname Bits
199 * Rev Fieldname Bits
221 * Rev Fieldname Bits
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| /linux/drivers/hwmon/pmbus/ |
| H A D | mp2888.c | 27 #define MP2888_TEMP_UNIT 10
28 #define MP2888_MAX_PHASE 10
57 * , bits 0-2. The value is selected as below: in mp2888_current_sense_gain_and_resolution_get()
58 * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A. Other in mp2888_current_sense_gain_and_resolution_get()
110 * register MP2888_MFR_VR_CONFIG1, bits 13-12 with the following selection of DrMOS in mp2888_read_phase()
112 * 00b - 8.5µA/A, 01b - 9.7µA/A, 1b - 10µA/A, 11b - 5µA/A. in mp2888_read_phase()
168 * provides 10 bits for mantissa and 6 bits for exponent. Bits 15:10 are set with in mp2888_read_word_data()
171 ret = (ret & GENMASK(9, 0)) | ((ret & GENMASK(31, 10)) << 1); in mp2888_read_word_data()
178 * Chip reports limits in degrees C, but the actual temperature in 10th of in mp2888_read_word_data()
191 * READ_IOUT register has unused bits 15:12 with fixed value 1110b. Clear these in mp2888_read_word_data()
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| /linux/arch/m68k/fpsp040/ |
| H A D | bindec.S | 13 | to 32-bits. The input may be either normalized,
31 | ILOG is the log base 10 of the input value. It is
53 | SCALE is equal to 10^ISCALE, where ISCALE is the number
57 | 10^^(abs(ISCALE)) using a rounding mode which is a
64 | only one rounding error. The grs bits are collected in
89 | result is exactly 10^LEN, decrement ILOG and divide
90 | the mantissa by 10.
95 | to be a fraction; i.e. (mantissa)/10^LEN and adjusted
106 | A16. Write sign bits to final string.
114 | d2: upper 32-bits of mantissa for binstr
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| H A D | do_func.S | 5 | to be performed is determined from the lower 7 bits of the
7 | The opcode and tag bits form an index into a jump table in
65 | unimplemented instructions. The test is on the upper 6 bits;
257 .long smod_fpn | 00,10 norm,inf = fpn
261 .long smod_zro | 01,10 zero,inf = +-zero
263 .long smod_oper | 10,00 inf,norm = nan with operr
264 .long smod_oper | 10,01 inf,zero = nan with operr
265 .long smod_oper | 10,10 inf,inf = nan with operr
266 .long smod_snan | 10,11 inf,nan = nan
269 .long smod_dnan | 11,10 nan,inf = nan
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| /linux/drivers/crypto/qce/ |
| H A D | regs-v5.h | 105 /* Register bits - REG_VERSION */
113 /* Register bits - REG_STATUS */
126 #define CRYPTO_STATE_SHIFT 10
127 #define CRYPTO_STATE_MASK GENMASK(13, 10)
139 /* Register bits - REG_STATUS2 */
143 /* Register bits - REG_CONFIG */
156 #define REQ_SIZE_ENUM_11_BEAT 10
169 #define IRQ_ENABLES_SHIFT 10
170 #define IRQ_ENABLES_MASK GENMASK(13, 10)
182 /* Register bits - REG_AUTH_SEG_CFG */
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| /linux/drivers/net/ethernet/apple/ |
| H A D | mace.h | 46 /* Bits in XMTFC */
51 /* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
61 /* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
65 /* Bits in RCVFC */
71 * Bits in RCVFS. After a frame is received, four bytes of status
84 /* Bits (fields) in FIFOFC */
91 * Bits in IR and IMR. The IR clears itself when read.
94 #define JABBER 0x80 /* jabber error - 10baseT xmission too long */
103 /* Bits in PR */
108 /* Bits in BIUCC */
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| /linux/drivers/net/wireless/zydas/zd1211rw/ |
| H A D | zd_rf_rf2959.c | 24 RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
32 static int bits(u32 rw, int from, int to)
41 return bits(rw, bit, bit);
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
54 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
62 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
63 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
67 bits(rw, 6, 17), bits(rw, 0, 5));
70 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
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| /linux/drivers/input/joystick/ |
| H A D | sidewinder.c | 37 #define SW_END 8 /* Number of bits before end of packet to kick */
41 #define SW_LENGTH 512 /* Max number of bits in a packet */
76 { 10, 10, 9, 10, 1, 1 },
78 { 10, 10, 6, 7, 1, 1 },
79 { 10, 10, 6, 7, 1, 1 },
80 { 10, 10, 6, 1, 1 },
81 { 10, 7, 7, 1, 1 }};
103 int bits; member
191 * sw_get_bits() and GB() compose bits from the triplet buffer into a __u64.
193 * of bits to be read, 'shift' is offset in the resulting __u64 to start at, bits
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| /linux/include/linux/mfd/atc260x/ |
| H A D | atc2603c.h | 201 /* PMU_SYS_CTL0 Register Mask Bits */
207 #define ATC2603C_PMU_SYS_CTL0_RESTART_EN BIT(10)
213 #define ATC2603C_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10)))
215 /* PMU_SYS_CTL1 Register Mask Bits */
225 #define ATC2603C_PMU_SYS_CTL1_ONOFF_PRESS_RESET_IRQ_PD BIT(10)
232 /* PMU_SYS_CTL2 Register Mask Bits */
240 #define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10)
246 /* PMU_SYS_CTL3 Register Mask Bits */
249 #define ATC2603C_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10)
254 /* PMU_SYS_CTL5 Register Mask Bits */
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| H A D | atc2609a.h | 228 /* PMU_SYS_CTL0 Register Mask Bits */
234 #define ATC2609A_PMU_SYS_CTL0_RESTART_EN BIT(10)
240 #define ATC2609A_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10)))
242 /* PMU_SYS_CTL1 Register Mask Bits */
252 #define ATC2609A_PMU_SYS_CTL1_RESTART_WK_FLAG BIT(10)
259 /* PMU_SYS_CTL2 Register Mask Bits */
267 #define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10)
273 /* PMU_SYS_CTL3 Register Mask Bits */
276 #define ATC2609A_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10)
281 /* PMU_SYS_CTL5 Register Mask Bits */
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