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/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c81 mdelay(10); in tx4927_pci_setup()
97 mdelay(10); in tx4927_pci_setup()
128 mdelay(10); in tx4937_pci_setup()
144 mdelay(10); in tx4937_pci_setup()
231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
235 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) in rbtx4927_clock_init()
236 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) in rbtx4927_clock_init()
237 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) in rbtx4927_clock_init()
238 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) in rbtx4927_clock_init()
239 * i.e. S9[3]: ON (83MHz), OFF (100MHz) in rbtx4927_clock_init()
[all …]
/linux/net/wireless/tests/
H A Dchan.c44 .desc = "identical 20 MHz",
53 .desc = "identical 40 MHz",
57 .center_freq1 = 5955 + 10,
62 .desc = "identical 80 MHz",
66 .center_freq1 = 5955 + 10 + 20,
71 .desc = "identical 160 MHz",
75 .center_freq1 = 5955 + 10 + 20 + 40,
80 .desc = "identical 320 MHz",
84 .center_freq1 = 5955 + 10 + 20 + 40 + 80,
89 .desc = "20 MHz in 320 MHz\n",
[all …]
/linux/drivers/clk/mvebu/
H A Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
66 - 8 MHz
[all …]
/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
31 10 10 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
H A Dr820t.c92 u32 bw; /* in MHz */
121 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
134 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
139 .freq = 50, /* Start freq, in MHz */
143 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
148 .freq = 55, /* Start freq, in MHz */
152 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
157 .freq = 60, /* Start freq, in MHz */
161 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
166 .freq = 65, /* Start freq, in MHz */
[all …]
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
/linux/net/mac80211/tests/
H A Dtpe.c34 .desc = "identical 20 MHz",
42 .desc = "identical 40 MHz",
50 .desc = "identical 80+80 MHz",
60 .desc = "identical 320 MHz",
68 .desc = "lower 160 MHz of 320 MHz",
76 .desc = "upper 160 MHz of 320 MHz",
84 .desc = "upper 160 MHz of 320 MHz, go to 40",
92 .desc = "secondary 80 above primary in 80+80 MHz",
102 .desc = "secondary 80 below primary in 80+80 MHz",
112 .desc = "secondary 80 below primary in 80+80 MHz, go to 20",
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
46 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
69 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
77 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
[all …]
/linux/Documentation/scsi/
H A Daic7xxx.rst26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
/linux/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h23 #define WL127X_MAJOR_SR_VER 10
36 #define WL128X_MAJOR_SR_VER 10
73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dchannel.c60 #define BRCM_2GHZ_2412_2462 REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
61 #define BRCM_2GHZ_2467_2472 REG_RULE(2467-10, 2472+10, 20, 0, 19, \
64 #define BRCM_5GHZ_5180_5240 REG_RULE(5180-10, 5240+10, 40, 0, 21, \
66 #define BRCM_5GHZ_5260_5320 REG_RULE(5260-10, 5320+10, 40, 0, 21, \
69 #define BRCM_5GHZ_5500_5700 REG_RULE(5500-10, 5700+10, 40, 0, 21, \
72 #define BRCM_5GHZ_5745_5825 REG_RULE(5745-10, 5825+10, 40, 0, 21, \
93 /* tx 20 MHz power limits, qdBm units */
95 /* tx 40 MHz power limits, qdBm units */
239 /* 20 MHz Legacy OFDM SISO */ in brcms_c_channel_min_txpower_limits_with_local_constraint()
243 /* 20 MHz Legacy OFDM CDD */ in brcms_c_channel_min_txpower_limits_with_local_constraint()
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf3 KernelVersion: v4.10
10 KernelVersion: v4.10
18 KernelVersion: v4.10
26 KernelVersion: v4.10
42 KernelVersion: v4.10
101 KernelVersion: v5.10
104 (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz,
105 when FIVR clock is 19.2MHz or 24MHz.
109 KernelVersion: v5.10
112 (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c146 feedback_divider *= 10; in calculate_fb_and_fractional_fb_divider()
147 /* additional factor, since we divide by 10 afterwards */ in calculate_fb_and_fractional_fb_divider()
149 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); in calculate_fb_and_fractional_fb_divider()
152 * The following code replace the old code (ullfeedbackDivider + 5)/10 in calculate_fb_and_fractional_fb_divider()
155 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ in calculate_fb_and_fractional_fb_divider()
161 calc_pll_cs->fract_fb_divider_precision_factor * 10); in calculate_fb_and_fractional_fb_divider()
218 actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10; in calc_fb_divider_checking_tolerance()
243 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); in calc_fb_divider_checking_tolerance()
314 calc_pll_cs->min_vco_khz * 10) { in calculate_pixel_clock_pll_dividers()
315 min_post_divider = calc_pll_cs->min_vco_khz * 10 / in calculate_pixel_clock_pll_dividers()
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c23 #define DLL_EN_MASK BIT(10)
27 #define SEL_FREQ_MASK GENMASK(12, 10)
59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu14_driver_if_v14_0.h56 #define FEATURE_DS_GFXCLK_BIT 10
205 #define THROTTLER_TEMP_LIQUID1_BIT 10
229 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
595 MEM_VENDOR_PLACEHOLDER1, // 10
703 #define PP_OD_FEATURE_FCLK_BIT 10
828 uint16_t UclkFmin; // MHz
829 uint16_t UclkFmax; // MHz
1030 uint16_t VftFMin; // in MHz
1062 uint8_t SocketPowerLimitSpare[10];
1140 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
[all …]
H A Dsmu11_driver_if_navi10.h83 #define FEATURE_DS_GFXCLK_BIT 10
184 #define THROTTLER_TEMP_PLX_BIT 10
465 #define HBM_DIE_TEMPERATURE_THROTTLING_BIT 10
585 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
586 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
587 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
588 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
589 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
590 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
591 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
[all …]
H A Dsmu13_driver_if_v13_0_7.h59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10
197 #define THROTTLER_TEMP_LIQUID0_BIT 10
222 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
691 #define PP_OD_FEATURE_TEMPERATURE_BIT 10
714 int16_t GfxclkFmin; // MHz
715 int16_t GfxclkFmax; // MHz
716 uint16_t UclkFmin; // MHz
717 uint16_t UclkFmax; // MHz
753 int16_t GfxclkFmin; // MHz
754 int16_t GfxclkFmax; // MHz
[all …]
/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/linux/drivers/clk/spear/
H A Dspear1310_clock.c46 #define SPEAR1310_GPT2_CLK_SHIFT 10
123 #define SPEAR1310_UHC1_CLK_ENB 10
156 #define SPEAR1310_PCLK0_CLK_ENB 10
190 #define SPEAR1310_UART1_CLK_SHIFT 10
215 #define SPEAR1310_UART1_CLK_ENB 10
231 /* PCLK 24MHz */
232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
[all …]
/linux/drivers/video/fbdev/
H A Dvalkyriefb.h11 * vmode 10 changed by Steven Borley <sjb@salix.demon.co.uk>, 14 mai 2000
79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
151 /* Register values for 800x600, 60Hz mode (10) */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.c68 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
70 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
72 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
73 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ …
74 …ine VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
83 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
84 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ
85 …15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB c…
124 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegratorap.dts31 * that the maximum frequency for this clock is 200 MHz
33 * is actually just hanging the system above 71 MHz.
59 /* 24 MHz chrystal on the Integrator/AP development board */
66 /* The UART clock is 14.74 MHz divided by an ICS525 */
75 /* 24 MHz chrystal on the core module */
92 /* Auxilary oscillator on the core module, 32.369MHz at boot */
123 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
182 /* IDSEL 10 */
183 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
184 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c39 #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10)
73 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
74 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_OFFSET 10
75 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
76 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
77 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
78 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
79 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
102 #define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10)
140 case 10 * MHZ: in exynos4x12_rate_to_clk()
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c124 if (enabled && factor != 1 && factor != 10) { in sja1105_cgu_idiv_config()
125 dev_err(dev, "idiv factor must be 1 or 10\n"); in sja1105_cgu_idiv_config()
130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
132 idiv.idiv = factor - 1; /* Divide by 1 or 10 */ in sja1105_cgu_idiv_config()
362 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
388 sja1105_packing(buf, &cmd->ctrl_ih, 10, 10, size, op); in sja1105_cfg_pad_mii_packing()
468 sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op); in sja1105_cfg_pad_mii_id_packing()
485 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
486 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
487 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
[all …]

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