Home
last modified time | relevance | path

Searched +full:1000 +full:mhz (Results 1 – 25 of 687) sorted by relevance

12345678910>>...28

/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/linux/drivers/clk/mvebu/
H A Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
55 [0x0] = 666 * 1000 * 1000,
56 [0x2] = 800 * 1000 * 1000,
57 [0x3] = 800 * 1000 * 1000,
58 [0x4] = 1066 * 1000 * 1000,
59 [0x5] = 1066 * 1000 * 1000,
60 [0x6] = 1200 * 1000 * 1000,
[all …]
H A Darmada-38x.c23 * 0 = 250 MHz
24 * 1 = 200 MHz
47 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
48 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
49 1332 * 1000 * 1000, 0, 0, 0,
50 1600 * 1000 * 1000, 0, 0, 0,
51 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
H A Dkirkwood.c28 * 4 = 600 MHz
29 * 6 = 800 MHz
30 * 7 = 1000 MHz
31 * 9 = 1200 MHz
32 * 12 = 1500 MHz
33 * 13 = 1600 MHz
34 * 14 = 1800 MHz
35 * 15 = 2000 MHz
54 * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
55 * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.c68 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
70 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
72 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
73 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ …
74 …ine VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
83 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
84 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ
85 …15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB c…
109 if (delay_us >= 1000) in dcn316_smu_wait_for_response()
[all …]
/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
119 table[i].frequency = freqs[i].cpufreq_mhz * 1000; in setup_freqs_table()
[all …]
H A Dimx6q-cpufreq.c69 freq_hz = new_freq * 1000; in imx6q_set_target()
70 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
83 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
84 old_freq / 1000, volt_old / 1000, in imx6q_set_target()
85 new_freq / 1000, volt / 1000); in imx6q_set_target()
124 * CPU may run at higher than 528MHz, this will lead to in imx6q_set_target()
126 * voltage of 528MHz, so lower the CPU frequency to one in imx6q_set_target()
129 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
140 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); in imx6q_set_target()
147 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); in imx6q_set_target()
[all …]
H A Dlongrun.c146 return eax * 1000; in longrun_get()
183 *low_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
188 *high_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
199 *high_freq = (cpu_khz / 1000); in longrun_determine_freqs()
200 *high_freq = *high_freq * 1000; in longrun_determine_freqs()
221 /* read out current core MHz and current perf_pctg */ in longrun_determine_freqs()
227 pr_debug("percentage is %u %%, freq is %u MHz\n", ecx, eax); in longrun_determine_freqs()
235 ebx = (((cpu_khz / 1000) * ecx) / 100); /* to MHz */ in longrun_determine_freqs()
241 *low_freq = edx * 1000; /* back to kHz */ in longrun_determine_freqs()
H A Dpxa2xx-cpufreq.c42 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
173 pxa27x_maxfreq *= 1000; in pxa27x_guess_max_freq()
181 return (unsigned int) clk_get_rate(data->clk_core) / 1000; in pxa_cpufreq_get()
198 pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n", in pxa_set_target()
199 policy->cur / 1000, new_freq_cpu / 1000); in pxa_set_target()
207 clk_set_rate(data->clk_core, new_freq_cpu * 1000); in pxa_set_target()
238 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ in pxa_cpufreq_init()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
[all …]
/linux/arch/arm/mach-s3c/
H A Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/linux/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
65 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
85 # MAIN (ALL UNITS IN MHZ)
95 min_freq=$((_min_freq / 1000))
97 max_freq=$((_max_freq / 1000))
103 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
[all …]
/linux/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
434 clos min is not specified, default: 0 MHz
[all …]
/linux/arch/x86/kvm/vmx/
H A Dtdx_arch.h127 * TDX requires the frequency to be defined in units of 25MHz, which is the
129 * module can only program frequencies that are multiples of 25MHz. The
130 * frequency must be between 100mhz and 10ghz (inclusive).
132 #define TDX_TSC_KHZ_TO_25MHZ(tsc_in_khz) ((tsc_in_khz) / (25 * 1000))
133 #define TDX_TSC_25MHZ_TO_KHZ(tsc_in_25mhz) ((tsc_in_25mhz) * (25 * 1000))
134 #define TDX_MIN_TSC_FREQUENCY_KHZ (100 * 1000)
135 #define TDX_MAX_TSC_FREQUENCY_KHZ (10 * 1000 * 1000)
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/linux/drivers/media/dvb-frontends/
H A Dtda826x.c73 div = (p->frequency + (1000-1)) / 1000; in tda826x_set_params()
75 /* BW = ((1 + RO) * SR/2 + 5) * 1.3 [SR in MSPS, BW in MHz] */ in tda826x_set_params()
77 ksyms = p->symbol_rate / 1000; in tda826x_set_params()
88 buf[2] = (1<<5) | 0x0b; // 1Mhz + 0.45 VCO in tda826x_set_params()
106 priv->frequency = div * 1000; in tda826x_set_params()
121 .frequency_min_hz = 950 * MHz,
122 .frequency_max_hz = 2175 * MHz
H A Dhorus3a.c170 u32 symbol_rate = p->symbol_rate/1000; in horus3a_set_params()
186 /* frequency should be X MHz (X : integer) */ in horus3a_set_params()
187 frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000; in horus3a_set_params()
195 /* Assumed that fREF == 1MHz (1000kHz) */ in horus3a_set_params()
196 ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000); in horus3a_set_params()
309 priv->frequency = ms * 2 * 1000 / mixdiv; in horus3a_set_params()
324 .frequency_min_hz = 950 * MHz,
325 .frequency_max_hz = 2150 * MHz,
326 .frequency_step_hz = 1 * MHz,
H A Dhelene.c54 /**< System-M (Japan) (IF: Fp=5.75MHz in default) */
56 /**< System-M (US) (IF: Fp=5.75MHz in default) */
58 /**< System-M (Korea) (IF: Fp=5.9MHz in default) */
60 /**< System-B/G (IF: Fp=7.3MHz in default) */
62 /**< System-I (IF: Fp=7.85MHz in default) */
64 /**< System-D/K (IF: Fp=7.85MHz in default) */
66 /**< System-L (IF: Fp=7.85MHz in default) */
68 /**< System-L DASH (IF: Fp=2.2MHz in default) */
71 /**< ATSC 8VSB (IF: Fc=3.7MHz in default) */
73 /**< US QAM (IF: Fc=3.7MHz in default) */
[all …]
/linux/tools/power/cpupower/utils/helpers/
H A Dmisc.c250 else if (speed > 1000) in print_speed()
251 printf("%u.%03u MHz", ((unsigned int)speed / 1000), in print_speed()
252 (unsigned int)(speed % 1000)); in print_speed()
263 tmp = speed % 1000; in print_speed()
265 speed += 1000; in print_speed()
266 printf("%u MHz", ((unsigned int)speed / 1000)); in print_speed()
267 } else if (speed > 1000) { in print_speed()
271 printf("%u.%01u MHz", ((unsigned int)speed / 1000), in print_speed()
272 ((unsigned int)(speed % 1000) / 100)); in print_speed()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c94 if (delay_us >= 1000) in dcn31_smu_wait_for_response()
95 msleep(delay_us/1000); in dcn31_smu_wait_for_response()
121 /* Set the parameter register for the SMU message, unit is Mhz */ in dcn31_smu_send_msg_with_param()
163 /* Unit of SMU msg parameter is Mhz */ in dcn31_smu_set_dispclk()
169 return actual_dispclk_set_mhz * 1000; in dcn31_smu_set_dispclk()
186 return actual_dprefclk_set_mhz * 1000; in dcn31_smu_set_dprefclk()
204 return actual_dcfclk_set_mhz * 1000; in dcn31_smu_set_hard_min_dcfclk()
222 return actual_min_ds_dcfclk_mhz * 1000; in dcn31_smu_set_min_deep_sleep_dcfclk()
237 return actual_dppclk_set_mhz * 1000; in dcn31_smu_set_dppclk()
349 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
/linux/drivers/phy/nuvoton/
H A Dphy-ma35d1-usb2.c22 #define PHY0DEVCKSTB BIT(10) /* PHY 60 MHz UTMI clock stable bit */
46 * make sure USB PHY 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
49 val & PHY0DEVCKSTB, 10, 1000); in ma35_usb_phy_power_on()
56 * wait until USB PHY0 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
64 /* make sure USB PHY 60 MHz UTMI Interface Clock ready */ in ma35_usb_phy_power_on()
66 val & PHY0DEVCKSTB, 10, 1000); in ma35_usb_phy_power_on()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c110 if (delay_us >= 1000) in dcn314_smu_wait_for_response()
111 msleep(delay_us/1000); in dcn314_smu_wait_for_response()
137 /* Set the parameter register for the SMU message, unit is Mhz */ in dcn314_smu_send_msg_with_param()
182 /* Unit of SMU msg parameter is Mhz */ in dcn314_smu_set_dispclk()
188 return actual_dispclk_set_mhz * 1000; in dcn314_smu_set_dispclk()
205 return actual_dprefclk_set_mhz * 1000; in dcn314_smu_set_dprefclk()
223 return actual_dcfclk_set_mhz * 1000; in dcn314_smu_set_hard_min_dcfclk()
241 return actual_min_ds_dcfclk_mhz * 1000; in dcn314_smu_set_min_deep_sleep_dcfclk()
256 return actual_dppclk_set_mhz * 1000; in dcn314_smu_set_dppclk()
388 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
/linux/drivers/pwm/
H A Dpwm-visconti.c11 * - The fixed input clock is running at 1 MHz and is divided by either 1,
58 * (0xffff << 3) * 1000 ns in visconti_pwm_apply()
62 if (state->period > (0xffff << 3) * 1000) in visconti_pwm_apply()
63 period = (0xffff << 3) * 1000; in visconti_pwm_apply()
73 * The input clock runs fixed at 1 MHz, so we have only in visconti_pwm_apply()
75 * NSEC_PER_SEC / CLKFREQ = 1000 without losing precision. in visconti_pwm_apply()
77 period /= 1000; in visconti_pwm_apply()
78 duty_cycle /= 1000; in visconti_pwm_apply()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c89 if (delay_us >= 1000) in dcn301_smu_wait_for_response()
90 msleep(delay_us/1000); in dcn301_smu_wait_for_response()
116 /* Set the parameter register for the SMU message, unit is Mhz */ in dcn301_smu_send_msg_with_param()
151 /* Unit of SMU msg parameter is Mhz */ in dcn301_smu_set_dispclk()
157 return actual_dispclk_set_mhz * 1000; in dcn301_smu_set_dispclk()
164 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
173 return actual_dprefclk_set_mhz * 1000; in dcn301_smu_set_dprefclk()
187 return actual_dcfclk_set_mhz * 1000; in dcn301_smu_set_hard_min_dcfclk()
201 return actual_min_ds_dcfclk_mhz * 1000; in dcn301_smu_set_min_deep_sleep_dcfclk()
215 return actual_dppclk_set_mhz * 1000; in dcn301_smu_set_dppclk()

12345678910>>...28