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/linux/include/uapi/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
26 #define SPEED_1000 1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
[all …]
/linux/drivers/watchdog/
H A Dmt7621_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Ralink MT7621/MT7628 built-in hardware watchdog timer
35 void __iomem *base; member
47 static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val) in rt_wdt_w32() argument
49 iowrite32(val, base + reg); in rt_wdt_w32()
52 static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg) in rt_wdt_r32() argument
54 return ioread32(base + reg); in rt_wdt_r32()
61 rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); in mt7621_wdt_ping()
66 static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) in mt7621_wdt_set_timeout() argument
70 w->timeout = t; in mt7621_wdt_set_timeout()
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H A Drti_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * (c) Copyright 2019-2020 Texas Instruments Inc.
27 #define MAX_HEARTBEAT 1000
68 * @base - base io address of WD device
69 * @freq - source clock frequency of WDT
70 * @wdd - hold watchdog device as is in WDT core
73 void __iomem *base; member
84 ret = pm_runtime_resume_and_get(wdd->parent); in rti_wdt_start()
89 timer_margin = (u64)wdd->timeout * wdt->freq; in rti_wdt_start()
93 writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD); in rti_wdt_start()
[all …]
/linux/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
66 * between 100T-full and 100T-half. If your phy does not support
90 * @duplex_lock: Non-zero if duplex is locked at full
196 * MII_CTRL1000 register when in 1000T mode.
216 * MII_CTRL1000 register when in 1000T mode.
238 * bits, when in 1000Base-T mode, to ethtool
258 * bits, when in 1000Base-T mode, to ethtool
276 * bits, when in 1000Base-T mode, to ethtool
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MII_GBCR 9 /* 1000Base-T control register */
19 #define MII_GBSR 10 /* 1000Base-T status register */
21 /* 1000Base-T control register fields */
28 /* 1000Base-T status register fields */
/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
99 * facilitate bug detection; even if we didn't boot from ROM.
258 /* Define chip-selects as reserved by default until probe completes */
299 rate /= 1000; in gpmc_get_fclk_period()
306 * gpmc_get_clk_period - get period of selected clock domain in ps
[all …]
/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
[all …]
/linux/sound/core/seq/
H A Dseq_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 1998-1999 by Frank van de Pol <fvdpol@coil.demon.nl>
17 #define DEFAULT_FREQUENCY 1000
24 tmr->tempo_base == 1000 ? 1000000 : 10000; in snd_seq_timer_set_tick_resolution()
26 if (tmr->temp in snd_seq_timer_set_tick_resolution()
63 struct snd_seq_timer *t = *tmr; snd_seq_timer_delete() local
228 snd_seq_timer_set_skew(struct snd_seq_timer * tmr,unsigned int skew,unsigned int base) snd_seq_timer_set_skew() argument
245 struct snd_timer_instance *t; snd_seq_timer_open() local
301 struct snd_timer_instance *t; snd_seq_timer_close() local
336 struct snd_timer *t; initialize_timer() local
[all...]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
45 struct dss_device *dss = pll->dss; in dss_pll_unregister()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
[all …]
/linux/drivers/leds/
H A Dleds-lm3533.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * leds-lm3533.c -- LM3533 LED driver
5 * Copyright (C) 2011-2012 Texas Instruments
61 return led->id + 2; in lm3533_led_get_ctrlbank_id()
64 static inline u8 lm3533_led_get_lv_reg(struct lm3533_led *led, u8 base) in lm3533_led_get_lv_reg() argument
66 return base + led->id; in lm3533_led_get_lv_reg()
71 return led->id; in lm3533_led_get_pattern()
75 u8 base) in lm3533_led_get_pattern_reg() argument
77 return base + lm3533_led_get_pattern(led) * LM3533_REG_PATTERN_STEP; in lm3533_led_get_pattern_reg()
88 dev_dbg(led->cdev.dev, "%s - %d\n", __func__, enable); in lm3533_led_pattern_enable()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
246 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
258 #define SPEED_1000 1000
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
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H A Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
[all …]
H A Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c50 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
53 (clk_mgr->regs->reg)
57 #define BASE(seg) BASE_INNER(seg) macro
60 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
88 /* fine-grained, only min and max */ in dcn3_init_single_clock()
98 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
105 dcn3_fpu_build_wm_range_table(&clk_mgr->base); in dcn3_build_wm_range_table()
114 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
115 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
116 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks()
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
30 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
31 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
34 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
35 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
41 /* connector doesn't config any color_format, use RGB444 as default */ in komeda_crtc_get_color_config()
53 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
54 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
58 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
61 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
[all …]
/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
201 .parent_names = (const char *[]){ "TBG-A-P", \
202 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
211 .parent_names = (const char *[]){ "TBG-A-P", \
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
59 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
[all …]
/linux/net/ethtool/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
20 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
22 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
23 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
25 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
26 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
27 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
54 const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; in __cvmx_helper_sgmii_hardware_init_one_time()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
45 CTX->logger
83 * won't work with REG_WAIT.
94 if (delay_us >= 1000) in dcn31_smu_wait_for_response()
95 msleep(delay_us/1000); in dcn31_smu_wait_for_response()
98 } while (max_retries--); in dcn31_smu_wait_for_response()
115 return -1; in dcn31_smu_send_msg_with_param()
136 return -1; in dcn31_smu_send_msg_with_param()
158 int actual_dispclk_set_mhz = -1; in dcn31_smu_set_dispclk()
160 if (!clk_mgr->smu_present) in dcn31_smu_set_dispclk()
[all …]

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