Home
last modified time | relevance | path

Searched +full:1000 +full:base +full:- +full:x +full:- +full:to +full:- +full:1000 +full:base +full:- +full:t (Results 1 – 25 of 716) sorted by relevance

12345678910>>...29

/linux/include/uapi/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
51 #define BMCR_RESET 0x8000 /* Reset to default state */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
19 MAC, while second one is SGMII for connection to MAC or fiber.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
[all …]
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
[all …]
/linux/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
65 * The one exception to IEEE 802.3u is that 100baseT4 is placed
66 * between 100T-full and 100T-half. If your phy does not support
68 * priority order, you will need to roll your own function.
90 * @duplex_lock: Non-zero if duplex is locked at full
112 * settings to phy autonegotiation advertisements for the
140 * settings to phy autonegotiation advertisements for the
168 * to ethtool advertisement settings.
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
30 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
31 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
34 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
35 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
41 /* connector doesn't config any color_format, use RGB444 as default */ in komeda_crtc_get_color_config()
53 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
54 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
58 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
61 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
[all …]
/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
97 * The first 1MB of GPMC address space is typically mapped to
98 * the internal ROM. Never allocate the first page, to
99 * facilitate bug detection; even if we didn't boot from ROM.
207 /* Structure to save gpmc cs context */
[all …]
/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
8 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
43 #define USBCFG_FLA(x) (((x) & 0x3f) << 8) argument
74 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
75 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
76 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
59 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
[all …]
/linux/drivers/leds/
H A Dleds-lm3533.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * leds-lm3533.c -- LM3533 LED driver
5 * Copyright (C) 2011-2012 Texas Instruments
61 return led->id + 2; in lm3533_led_get_ctrlbank_id()
64 static inline u8 lm3533_led_get_lv_reg(struct lm3533_led *led, u8 base) in lm3533_led_get_lv_reg() argument
66 return base + led->id; in lm3533_led_get_lv_reg()
71 return led->id; in lm3533_led_get_pattern()
75 u8 base) in lm3533_led_get_pattern_reg() argument
77 return base + lm3533_led_get_pattern(led) * LM3533_REG_PATTERN_STEP; in lm3533_led_get_pattern_reg()
88 dev_dbg(led->cdev.dev, "%s - %d\n", __func__, enable); in lm3533_led_pattern_enable()
[all …]
/linux/sound/core/seq/
H A Dseq_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 1998-1999 by Frank van de Pol <fvdpol@coil.demon.nl>
17 #define DEFAULT_FREQUENCY 1000
24 tmr->tempo_base == 1000 ? 1000000 : 10000; in snd_seq_timer_set_tick_resolution()
26 if (tmr->temp in snd_seq_timer_set_tick_resolution()
63 struct snd_seq_timer *t = *tmr; snd_seq_timer_delete() local
228 snd_seq_timer_set_skew(struct snd_seq_timer * tmr,unsigned int skew,unsigned int base) snd_seq_timer_set_skew() argument
245 struct snd_timer_instance *t; snd_seq_timer_open() local
301 struct snd_timer_instance *t; snd_seq_timer_close() local
336 struct snd_timer *t; initialize_timer() local
[all...]
/linux/drivers/regulator/
H A Dtwl-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * twl-regulator.c -- support regulators in twl4030/twl6030 family chips
25 * These chips are often used in OMAP-based systems.
27 * This driver implements software-based resource control for various
34 u8 base; member
39 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
57 /* LDO control registers ... offset is from the base of its register bank.
58 * The first three registers of all power resource banks help hardware to
81 &value, info->base + offset); in twlreg_read()
90 value, info->base + offset); in twlreg_write()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
48 CTX->logger
76 * Function to be used instead of REG_WAIT macro because the wait ends when
77 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
78 * won't work with REG_WAIT.
[all …]
/linux/drivers/net/phy/
H A Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/mdio/mdio-i2c.h>
149 "mod-def0",
151 "tx-fault",
152 "tx-disable",
153 "rate-select0",
154 "rate-select1",
166 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
167 * non-cooled module to initialise its laser safety circuitry. We wait
168 * an initial T_WAIT period before we check the tx fault to give any PHY
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drs690.c6 * Permission is hereby granted, free of charge, to any person obtaining a
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42 for (i = 0; i < rdev->usec_timeout; i++) { in rs690_mc_wait_for_idle()
49 return -1; in rs690_mc_wait_for_idle()
57 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); in rs690_gpu_init()
74 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, in rs690_pm_info()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
161 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
162 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
168 /* Link Partner Ability Register (Base Page) */
172 /* 1000BASE-T Control Register */
173 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
174 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
176 /* 1000BASE-T Status Register */
181 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
[all …]
/linux/drivers/spi/
H A Dspi-sprd-adi.c4 * SPDX-License-Identifier: GPL-2.0
36 #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
77 #define ADI_FIFO_DRAIN_TIMEOUT 1000
81 * Read back address from REG_ADI_RD_DATA bit[30:16] which maps to:
125 /* Use default timeout 50 ms that converts to watchdog values */
126 #define WDG_LOAD_VAL ((50 * 32768) / 1000)
131 u32 base; member
148 void __iomem *base; member
157 if (reg >= sadi->data->slave_addr_size) { in sprd_adi_check_addr()
158 dev_err(sadi->dev, in sprd_adi_check_addr()
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/linux/drivers/scsi/pcmcia/
H A Dnsp_cs.c3 NinjaSCSI-3 / NinjaSCSI-32Bi PCMCIA SCSI host adapter card driver
13 This software may be used and distributed according to the terms of
21 I-O DATA PCSC-F (Workbit NinjaSCSI-3)
22 "WBT", "NinjaSCSI-3", "R1.0"
23 I-O DATA CBSC-II (Workbit NinjaSCSI-32Bi in 16bit mode)
56 MODULE_DESCRIPTION("WorkBit NinjaSCSI-3 / NinjaSCSI-32Bi(16bit) PCMCIA SCSI host adapter module");
81 .name = "WorkBit NinjaSCSI-3/32Bi(16bit)",
90 .dma_boundary = PAGE_SIZE - 1,
94 static nsp_hw_data nsp_data_base; /* attach <-> detect glue */
169 printk("nsp_cs-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); in nsp_cs_dmessage()
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
47 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
53 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
60 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
74 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
75 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
76 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
78 snprintf(mpcs->name, sizeof(mpcs->name), in mv88e639x_pcs_alloc()
79 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port); in mv88e639x_pcs_alloc()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
206 /* Initiate an interrupt to manageability engine */
246 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
[all …]
/linux/drivers/i2c/busses/
H A Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
8 * to the automotive development board Russellville. The copyright holder
11 * separate company called Pelagicore AB, which committed the code to the
27 #include <linux/platform_data/i2c-xiic.h>
36 #define DRIVER_NAME "xiic-i2c"
58 * struct xiic_i2c - Internal representation of the XIIC I2C bus
59 * @dev: Pointer to device structure
[all …]
/linux/net/ethtool/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
20 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
22 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
23 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
25 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
26 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
27 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
[all …]

12345678910>>...29