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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
129 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
149 #define PIPE_REG_RESET BIT(1)
160 #define BUNDLE_PERIOD_SEL BIT(1)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
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H A Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 * row index = serdes lane,
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
69 if (priv->conf) { in a38x_set_conf()
70 conf = readl_relaxed(priv->conf); in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
75 writel(conf, priv->conf); in a38x_set_conf()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
32 #define HSIO_APB_RSTN_1 BIT(1)
45 #define HSIO_IOB_TXENA BIT(1)
96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
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H A Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
61 /* Lane a Tx General Control Register */
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
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/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
29 #define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */
30 #define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */
74 #define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0)
80 #define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1)
81 #define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
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H A Dbxt_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
16 _PICK_EVEN_2RANGES(phy, 1, \
21 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
24 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
25 (reg_ch1) - _BXT_PHY0_BASE))
28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
89 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
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/linux/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
17 #define SDW_STRM_RATE_GROUPING 1
21 unsigned int lane; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
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/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
46 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
47 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
48 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
55 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
65 USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
67 SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \
72 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
73 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
74 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
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H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
35 #define PORT_XUSB 1
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
99 #define HSIC_PD_TX_DATA0 BIT(1)
128 #define CAP_CFG BIT(1)
139 #define UTMI_FS SPEED(1)
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H A Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
19 /* legacy entry points for backwards-compatibility */
55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
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/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
18 maxItems: 1
20 vcc-supply:
23 enable-gpios: true
24 orientation-switch: true
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
4 // tegra186_asrc.c - Tegra186 ASRC driver
30 (((id) + 1) << 4) }, \
44 ASRC_STREAM_REG_DEFAULTS(1),
72 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
75 1); in tegra186_asrc_lock_stream()
82 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
83 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
93 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
30 * Lane Registers
33 /* TX De-emphasis parameters */
46 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
149 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
163 /* Lane 0/1/2/3 offset */
174 /* Lane 0/1/2/3 Register */
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
73 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
75 if (!dp->force_hpd) in analogix_dp_detect_hpd()
76 return -ETIMEDOUT; in analogix_dp_detect_hpd()
83 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
88 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
89 return -EINVAL; in analogix_dp_detect_hpd()
92 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
102 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
103 if (ret != 1) { in analogix_dp_detect_sink_psr()
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/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
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/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
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/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 switch (dp->link.cap.link_rate) { in hibmc_dp_get_serdes_rate_cfg()
24 return -EINVAL; in hibmc_dp_get_serdes_rate_cfg()
33 /* DP 2 lane */ in hibmc_dp_link_training_configure()
35 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
37 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
42 /* set rate and lane count */ in hibmc_dp_link_training_configure()
43 buf[0] = dp->link.cap.link_rate; in hibmc_dp_link_training_configure()
44 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
45 ret = drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); in hibmc_dp_link_training_configure()
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/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
26 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
27 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
28 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
37 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
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/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define PHY_SUBMODE_EDP 1
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
34 * lane 0, used for the transmissions on main link.
36 * Allowed values: 1, 2, 4
44 * to be used by particular lanes. One value per lane.
45 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
55 * used by particular lanes. One value per lane.
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
20 maxItems: 1
22 "#phy-cells":
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
24 #define TXC_LOOPBACKS ((1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
26 (1 << LOOPBACK_PHYXS_WS))
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
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