| /linux/drivers/isdn/mISDN/ |
| H A D | layer2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
59 #define L2_EVENT_COUNT (EV_L2_FRAME_ERROR + 1)
92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
[all …]
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| H A D | tei.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #define ID_REQUEST 1
39 #define DEACT_STATE_COUNT (ST_L1_ACTIV + 1)
57 #define DEACT_EVENT_COUNT (EV_DATIMER + 1)
72 struct manager *mgr = fi->userdata; in da_debug()
84 printk(KERN_DEBUG "mgr(%d): %pV\n", mgr->ch.st->dev->id, &vaf); in da_debug()
92 struct manager *mgr = fi->userdata; in da_activate()
94 if (fi->state == ST_L1_DEACT_PENDING) in da_activate()
95 mISDN_FsmDelTimer(&mgr->datimer, 1); in da_activate()
108 struct manager *mgr = fi->userdata; in da_deactivate()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
33 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
37 "BriefDescription": "L2 cache request misses",
38 "Counter": "0,1,2,3",
41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
46 "BriefDescription": "L2 cache requests",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
33 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
37 "BriefDescription": "L2 cache request misses",
38 "Counter": "0,1,2,3",
41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
46 "BriefDescription": "L2 cache requests",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
25 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
32 "CounterMask": "1",
39 "AnyThread": "1",
42 "CounterMask": "1",
50 "Counter": "0,1,2,3",
57 "BriefDescription": "Not rejected writebacks that hit L2 cache",
58 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
25 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
32 "CounterMask": "1",
40 "AnyThread": "1",
43 "CounterMask": "1",
50 "BriefDescription": "Not rejected writebacks that hit L2 cache",
51 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
26 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
33 "CounterMask": "1",
40 "AnyThread": "1",
43 "CounterMask": "1",
51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
52 "Counter": "0,1,2,3",
59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | cache.json | 3 …at were not accepted into the L2Q because of any L2 queue reject condition. There is no concept o…
4 "Counter": "0,1",
11 "Counter": "0,1",
19 "Counter": "0,1",
26 "BriefDescription": "Counts the number of L2 cache misses",
27 "Counter": "0,1",
34 "BriefDescription": "Counts the total number of L2 cache references.",
35 "Counter": "0,1",
42 …ing SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC)…
43 "Counter": "0,1",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
25 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
32 "CounterMask": "1",
39 "AnyThread": "1",
42 "CounterMask": "1",
50 "Counter": "0,1,2,3",
57 "BriefDescription": "Not rejected writebacks that hit L2 cache",
58 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
25 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
32 "CounterMask": "1",
40 "AnyThread": "1",
43 "CounterMask": "1",
50 "BriefDescription": "Not rejected writebacks that hit L2 cache",
51 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
15 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
31 "CounterMask": "1",
32 "EdgeDetect": "1",
40 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
41 "Counter": "0,1,2,3",
44 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
26 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
33 "CounterMask": "1",
40 "AnyThread": "1",
43 "CounterMask": "1",
51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
52 "Counter": "0,1,2,3",
59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
33 "Counter": "0,1,2,3",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
42 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
15 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
31 "CounterMask": "1",
32 "EdgeDetect": "1",
41 "Counter": "0,1,2,3",
42 "Deprecated": "1",
49 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
15 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
31 "CounterMask": "1",
32 "EdgeDetect": "1",
41 "Counter": "0,1,2,3",
42 "Deprecated": "1",
49 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | cache.json | 4 "Counter": "0,1",
7 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
11 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
12 "Counter": "0,1",
20 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
21 "Counter": "0,1",
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
28 "BriefDescription": "L2 cache request misses",
29 "Counter": "0,1",
32 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
16 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
23 "Counter": "0,1,2,3",
33 "Counter": "0,1,2,3",
34 "CounterMask": "1",
35 "EdgeDetect": "1",
44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
45 "Counter": "0,1,2,3",
48 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
33 "Counter": "0,1,2,3",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
42 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | cache.json | 5 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
6 …ip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads…
11 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
12 …ip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads…
18 … Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …he was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetch…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load…
36 …ation other than the local core's L2 due to either only demand loads or demand loads plus prefetch…
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
33 "Counter": "0,1,2,3",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
42 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
33 "Counter": "0,1,2,3",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
42 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | cache.json | 3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a…
4 "Counter": "0,1,2,3",
7 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
24 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 …
28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
29 "Counter": "0,1,2,3",
32 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request…
36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe…
[all …]
|