Lines Matching +full:1 +full:- +full:l2
4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
33 "Counter": "0,1,2,3",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
42 "Counter": "0,1,2,3",
45 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
51 "Counter": "0,1,2,3",
52 "CounterMask": "1",
60 "BriefDescription": "L2 cache lines filling L2",
61 "Counter": "0,1,2,3",
64 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
69 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
70 "Counter": "0,1,2,3",
73 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
78 "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
79 "Counter": "0,1,2,3",
82 …r of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive…
87 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce…
88 "Counter": "0,1,2,3",
91 …ines that have been prefetched by the L2 hardware prefetcher but not used by demand access when ev…
96 "BriefDescription": "L2 code requests",
97 "Counter": "0,1,2,3",
100 "PublicDescription": "Counts the total number of L2 code requests.",
106 "Counter": "0,1,2,3",
109 …uding requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non reje…
114 "BriefDescription": "Demand requests that miss L2 cache",
115 "Counter": "0,1,2,3",
118 "PublicDescription": "Counts demand requests that miss L2 cache.",
123 "BriefDescription": "Demand requests to L2 cache",
124 "Counter": "0,1,2,3",
127 "PublicDescription": "Counts demand requests to L2 cache.",
132 "BriefDescription": "RFO requests to L2 cache",
133 "Counter": "0,1,2,3",
136 …on": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests in…
141 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
142 "Counter": "0,1,2,3",
145 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
150 "BriefDescription": "L2 cache misses when fetching instructions",
151 "Counter": "0,1,2,3",
154 "PublicDescription": "Counts L2 cache misses when fetching instructions.",
159 "BriefDescription": "Demand Data Read requests that hit L2 cache",
160 "Counter": "0,1,2,3",
163 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
168 "BriefDescription": "Demand Data Read miss L2, no rejects",
169 "Counter": "0,1,2,3",
172 …"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not …
177 "BriefDescription": "All requests that miss L2 cache.",
178 "Counter": "0,1,2,3",
181 "PublicDescription": "Counts all requests that miss L2 cache.",
186 "BriefDescription": "All L2 requests.",
187 "Counter": "0,1,2,3",
190 "PublicDescription": "Counts all L2 requests.",
195 "BriefDescription": "RFO requests that hit L2 cache",
196 "Counter": "0,1,2,3",
199 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
204 "BriefDescription": "RFO requests that miss L2 cache",
205 "Counter": "0,1,2,3",
208 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
213 "BriefDescription": "SW prefetch requests that hit L2 cache.",
214 "Counter": "0,1,2,3",
217 …": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCH…
222 "BriefDescription": "SW prefetch requests that miss L2 cache.",
223 "Counter": "0,1,2,3",
226 …: "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCH…
231 "BriefDescription": "L2 writebacks that access L2 cache",
232 "Counter": "0,1,2,3",
235 "PublicDescription": "Counts L2 writebacks that access L2 cache.",
240 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche…
241 "Counter": "0,1,2,3,4,5,6,7",
244 …-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include da…
250 "Counter": "0,1,2,3",
251 "Data_LA": "1",
254 …. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
260 "Counter": "0,1,2,3",
261 "Data_LA": "1",
270 "Counter": "0,1,2,3",
271 "Data_LA": "1",
274 "PublicDescription": "Counts all retired memory instructions - loads and stores.",
280 "Counter": "0,1,2,3",
281 "Data_LA": "1",
290 "Counter": "0,1,2,3",
291 "Data_LA": "1",
300 "Counter": "0,1,2,3",
301 "Data_LA": "1",
310 "Counter": "0,1,2,3",
311 "Data_LA": "1",
314 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
320 "Counter": "0,1,2,3",
321 "Data_LA": "1",
324 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
329 …: "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core c…
330 "Counter": "0,1,2,3",
331 "Data_LA": "1",
334 …ts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core c…
340 "Counter": "0,1,2,3",
341 "Data_LA": "1",
349 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
350 "Counter": "0,1,2,3",
351 "Data_LA": "1",
354 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
360 "Counter": "0,1,2,3",
361 "Data_LA": "1",
369 "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
370 "Counter": "0,1,2,3",
371 "Data_LA": "1",
374 …ired instructions with at least one load to uncacheable memory-type, or at least one cache-line sp…
380 "Counter": "0,1,2,3",
381 "Data_LA": "1",
390 "Counter": "0,1,2,3",
391 "Data_LA": "1",
400 "Counter": "0,1,2,3",
401 "Data_LA": "1",
409 "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
410 "Counter": "0,1,2,3",
411 "Data_LA": "1",
414 "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
419 "BriefDescription": "Retired load instructions missed L2 cache as data sources",
420 "Counter": "0,1,2,3",
421 "Data_LA": "1",
424 "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
430 "Counter": "0,1,2,3",
431 "Data_LA": "1",
440 "Counter": "0,1,2,3",
441 "Data_LA": "1",
450 "Counter": "0,1,2,3",
460 "Counter": "0,1,2,3",
470 "Counter": "0,1,2,3",
480 "Counter": "0,1,2,3",
490 "Counter": "0,1,2,3",
500 "Counter": "0,1,2,3",
510 "Counter": "0,1,2,3",
520 "Counter": "0,1,2,3",
530 "Counter": "0,1,2,3",
540 "Counter": "0,1,2,3",
550 "Counter": "0,1,2,3",
560 "Counter": "0,1,2,3",
570 "Counter": "0,1,2,3",
580 "Counter": "0,1,2,3",
590 "Counter": "0,1,2,3",
600 "Counter": "0,1,2,3",
610 "Counter": "0,1,2,3",
620 "Counter": "0,1,2,3",
630 "Counter": "0,1,2,3",
640 "Counter": "0,1,2,3",
650 "Counter": "0,1,2,3",
660 "Counter": "0,1,2,3",
670 "Counter": "0,1,2,3",
680 "Counter": "0,1,2,3",
690 "Counter": "0,1,2,3",
699 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any t…
700 "Counter": "0,1,2,3",
709 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach…
710 "Counter": "0,1,2,3",
719 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach…
720 "Counter": "0,1,2,3",
729 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach…
730 "Counter": "0,1,2,3",
739 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach…
740 "Counter": "0,1,2,3",
749 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach…
750 "Counter": "0,1,2,3",
759 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cach…
760 "Counter": "0,1,2,3",
769 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of …
770 "Counter": "0,1,2,3",
779 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline i…
780 "Counter": "0,1,2,3",
789 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline i…
790 "Counter": "0,1,2,3",
799 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline i…
800 "Counter": "0,1,2,3",
809 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline i…
810 "Counter": "0,1,2,3",
819 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline i…
820 "Counter": "0,1,2,3",
829 …"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline i…
830 "Counter": "0,1,2,3",
840 "Counter": "0,1,2,3",
849 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit…
850 "Counter": "0,1,2,3",
859 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit…
860 "Counter": "0,1,2,3",
869 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit…
870 "Counter": "0,1,2,3",
879 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit…
880 "Counter": "0,1,2,3",
890 "Counter": "0,1,2,3",
900 "Counter": "0,1,2,3",
903 …d prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 …
909 "Counter": "0,1,2,3",
918 "Counter": "0,1,2,3",
927 "Counter": "0,1,2,3",
936 "Counter": "0,1,2,3",
939 …L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page wal…
944 "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
945 "Counter": "0,1,2,3",
946 "CounterMask": "1",
949 …1 outstanding data read request is pending. Data read requests include cacheable demand reads and…
955 "Counter": "0,1,2,3",
956 "CounterMask": "1",
959 …clude both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the t…
964 "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
965 "Counter": "0,1,2,3",
966 "CounterMask": "1",
969 …1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data stor…
975 "Counter": "0,1,2,3",
978 …. Requests are considered outstanding from the time they miss the core's L2 cache until the tran…
983 "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
984 "Counter": "0,1,2,3",
987 …-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is c…
993 "Counter": "0,1,2,3",
1002 "Counter": "0,1,2,3",
1011 "Counter": "0,1,2,3",
1019 "Counter": "0,1,2,3",
1028 "Counter": "0,1,2,3",
1037 "Counter": "0,1,2,3",
1046 "Counter": "0,1,2,3",