| /freebsd/contrib/wpa/src/l2_packet/ |
| H A D | l2_packet_winpcap.c | 2 * WPA Supplicant - Layer2 packet handling with WinPcap RX thread
3 * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
24 * implement this kind of waiting with a simpler single-thread design. However,
65 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
67 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
72 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
78 if (l2 == NULL) in l2_packet_send()
79 return -1; in l2_packet_send()
81 if (l2->l2_hdr) { in l2_packet_send()
82 ret = pcap_sendpacket(l2->pcap, buf, len); in l2_packet_send()
[all …]
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| H A D | l2_packet_pcap.c | 2 * WPA Supplicant - Layer2 packet handling with libpcap/libdnet and WinPcap
3 * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
43 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
45 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
51 static int l2_packet_init_libdnet(struct l2_packet_data *l2) in l2_packet_init_libdnet() argument
55 l2->eth = eth_open(l2->ifname); in l2_packet_init_libdnet()
56 if (!l2->eth) { in l2_packet_init_libdnet()
58 "Failed to open interface '%s' - eth_open: %s", in l2_packet_init_libdnet()
59 l2->ifname, strerror(errno)); in l2_packet_init_libdnet()
60 return -1; in l2_packet_init_libdnet()
[all …]
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| H A D | l2_packet_privsep.c | 2 * WPA Supplicant - Layer2 packet handling with privilege separation
29 static int wpa_priv_cmd(struct l2_packet_data *l2, int cmd, in wpa_priv_cmd() argument
37 io[1].iov_base = (u8 *) data; in wpa_priv_cmd()
38 io[1].iov_len = data_len; in wpa_priv_cmd()
42 msg.msg_iovlen = data ? 2 : 1; in wpa_priv_cmd()
43 msg.msg_name = &l2->priv_addr; in wpa_priv_cmd()
44 msg.msg_namelen = sizeof(l2->priv_addr); in wpa_priv_cmd()
46 if (sendmsg(l2->fd, &msg, 0) < 0) { in wpa_priv_cmd()
47 wpa_printf(MSG_ERROR, "L2: sendmsg(cmd): %s", strerror(errno)); in wpa_priv_cmd()
48 return -1; in wpa_priv_cmd()
[all …]
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| H A D | l2_packet_linux.c | 2 * WPA Supplicant - Layer2 packet handling with Linux packet sockets
3 * Copyright (c) 2003-2015, Jouni Malinen <j@w1.fi>
24 char ifname[IFNAMSIZ + 1];
43 /* Generated by 'sudo tcpdump -s 3000 -dd greater 278 and ip and udp and
59 { 0x15, 0, 1, 0x00000044 },
70 /* Generated by 'sudo tcpdump -dd -s 1500 multicast and ip6[6]=58' */
77 { 0x15, 0, 1, 0x0000003a },
87 /* drop packet if skb->pkt_type is PACKET_OTHERHOST (0x03). Generated by:
88 * $ bpfc - <<EOF
91 * > pass: ret #-1
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| H A D | l2_packet_ndis.c | 2 * WPA Supplicant - Layer2 packet handling with Microsoft NDISUIO
3 * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
46 * fake support for two (EAPOL and RSN pre-auth) by switching to pre-auth
47 * whenever wpa_supplicant is trying to pre-authenticate and then switching
48 * back to EAPOL when pre-authentication has been completed.
56 struct l2_packet_data *l2[2]; member
84 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
86 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
91 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
102 if (l2 == NULL) in l2_packet_send()
[all …]
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| H A D | l2_packet_freebsd.c | 2 * WPA Supplicant - Layer2 packet handling with FreeBSD
3 * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
53 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
55 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
60 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
63 if (!l2->l2_hdr) { in l2_packet_send()
67 return -1; in l2_packet_send()
68 os_memcpy(eth->h_dest, dst_addr, ETH_ALEN); in l2_packet_send()
69 os_memcpy(eth->h_source, l2->own_addr, ETH_ALEN); in l2_packet_send()
70 eth->h_proto = htons(proto); in l2_packet_send()
[all …]
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| H A D | l2_packet_none.c | 2 * WPA Supplicant - Layer2 packet handling example with stub functions
3 * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
30 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
32 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
37 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
40 if (l2 == NULL) in l2_packet_send()
41 return -1; in l2_packet_send()
45 * whether l2->l2_hdr is set). in l2_packet_send()
54 struct l2_packet_data *l2 = eloop_ctx; in l2_packet_receive() local
62 l2->rx_callback(l2->rx_callback_ctx, NULL /* TODO: src addr */, in l2_packet_receive()
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| /freebsd/sys/powerpc/mpc85xx/ |
| H A D | mpc85xx_cache.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
41 * - mbar
42 * - isync
43 * - write
44 * - read
45 * - mbar
55 {"fsl,8540-l2-cache-controller", 1},
56 {"fsl,8541-l2-cache-controller", 1},
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| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 4 "CollectPEBSRecord": "1",
5 "Counter": "0,1,2,3",
13 "CollectPEBSRecord": "1",
14 "Counter": "0,1,2,3",
22 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
23 "CollectPEBSRecord": "1",
24 "Counter": "0,1,2,3",
33 "CollectPEBSRecord": "1",
34 "Counter": "0,1,2,3",
37 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/ |
| H A D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 4 "CollectPEBSRecord": "1",
5 "Counter": "0,1,2,3",
9 "PEBScounters": "0,1,2,3",
15 "CollectPEBSRecord": "1",
16 "Counter": "0,1,2,3",
20 "PEBScounters": "0,1,2,3",
26 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
27 "CollectPEBSRecord": "1",
28 "Counter": "0,1,2,3",
32 "PEBScounters": "0,1,2,3",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/knightslanding/ |
| H A D | cache.json | 3 …at were not accepted into the L2Q because of any L2 queue reject condition. There is no concept o…
4 "Counter": "0,1",
11 "Counter": "0,1",
19 "BriefDescription": "Counts the number of L2 cache misses",
20 "Counter": "0,1",
27 "BriefDescription": "Counts the total number of L2 cache references.",
28 "Counter": "0,1",
35 …ing SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC)…
36 "Counter": "0,1",
42 "BriefDescription": "Counts all the load micro-ops retired",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
36 "CounterMask": "1",
44 "AnyThread": "1",
48 "CounterMask": "1",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
29 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
37 "CounterMask": "1",
44 "AnyThread": "1",
48 "CounterMask": "1",
56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
36 "CounterMask": "1",
44 "AnyThread": "1",
48 "CounterMask": "1",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/haswell/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
28 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
36 "CounterMask": "1",
43 "AnyThread": "1",
47 "CounterMask": "1",
55 "Counter": "0,1,2,3",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/ |
| H A D | cache.json | 5 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
16 "Counter": "0,1,2,3",
19 "PEBScounters": "0,1,2,3",
27 "Counter": "0,1,2,3",
28 "CounterMask": "1",
29 "EdgeDetect": "1",
32 "PEBScounters": "0,1,2,3",
38 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
[all …]
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| /freebsd/lib/libpmc/ |
| H A D | pmc.corei7.3 | 6 .\" 1. Redistributions of source code must retain the above copyright
44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
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| /freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
29 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
37 "CounterMask": "1",
44 "AnyThread": "1",
48 "CounterMask": "1",
56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
28 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
36 "CounterMask": "1",
43 "AnyThread": "1",
47 "CounterMask": "1",
55 "Counter": "0,1,2,3",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/silvermont/ |
| H A D | cache.json | 4 "Counter": "0,1",
7 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
11 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
12 "Counter": "0,1",
20 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
21 "Counter": "0,1",
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
28 "BriefDescription": "L2 cache request misses",
29 "Counter": "0,1",
32 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
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| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
[all …]
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