Lines Matching +full:1 +full:- +full:l2
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
28 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
36 "CounterMask": "1",
43 "AnyThread": "1",
47 "CounterMask": "1",
55 "Counter": "0,1,2,3",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
63 "BriefDescription": "Not rejected writebacks that hit L2 cache",
64 "Counter": "0,1,2,3",
65 "CounterHTOff": "0,1,2,3,4,5,6,7",
68 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
73 "BriefDescription": "L2 cache lines filling L2",
74 "Counter": "0,1,2,3",
75 "CounterHTOff": "0,1,2,3,4,5,6,7",
78 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
83 "BriefDescription": "L2 cache lines in E state filling L2",
84 "Counter": "0,1,2,3",
85 "CounterHTOff": "0,1,2,3,4,5,6,7",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
93 "BriefDescription": "L2 cache lines in I state filling L2",
94 "Counter": "0,1,2,3",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
98 "PublicDescription": "L2 cache lines in I state filling L2.",
103 "BriefDescription": "L2 cache lines in S state filling L2",
104 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
108 "PublicDescription": "L2 cache lines in S state filling L2.",
113 "BriefDescription": "Clean L2 cache lines evicted by demand",
114 "Counter": "0,1,2,3",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
118 "PublicDescription": "Clean L2 cache lines evicted by demand.",
123 "BriefDescription": "Dirty L2 cache lines evicted by demand",
124 "Counter": "0,1,2,3",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
128 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
133 "BriefDescription": "L2 code requests",
134 "Counter": "0,1,2,3",
135 "CounterHTOff": "0,1,2,3,4,5,6,7",
138 "PublicDescription": "Counts all L2 code requests.",
144 "Counter": "0,1,2,3",
145 "CounterHTOff": "0,1,2,3,4,5,6,7",
149 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
154 "BriefDescription": "Demand requests that miss L2 cache",
155 "Counter": "0,1,2,3",
156 "CounterHTOff": "0,1,2,3,4,5,6,7",
160 "PublicDescription": "Demand requests that miss L2 cache.",
165 "BriefDescription": "Demand requests to L2 cache",
166 "Counter": "0,1,2,3",
167 "CounterHTOff": "0,1,2,3,4,5,6,7",
171 "PublicDescription": "Demand requests to L2 cache.",
176 "BriefDescription": "Requests from L2 hardware prefetchers",
177 "Counter": "0,1,2,3",
178 "CounterHTOff": "0,1,2,3,4,5,6,7",
181 "PublicDescription": "Counts all L2 HW prefetcher requests.",
186 "BriefDescription": "RFO requests to L2 cache",
187 "Counter": "0,1,2,3",
188 "CounterHTOff": "0,1,2,3,4,5,6,7",
191 "PublicDescription": "Counts all L2 store RFO requests.",
196 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
197 "Counter": "0,1,2,3",
198 "CounterHTOff": "0,1,2,3,4,5,6,7",
201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
206 "BriefDescription": "L2 cache misses when fetching instructions",
207 "Counter": "0,1,2,3",
208 "CounterHTOff": "0,1,2,3,4,5,6,7",
211 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
216 "BriefDescription": "Demand Data Read requests that hit L2 cache",
217 "Counter": "0,1,2,3",
218 "CounterHTOff": "0,1,2,3,4,5,6,7",
222 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
227 "BriefDescription": "Demand Data Read miss L2, no rejects",
228 "Counter": "0,1,2,3",
229 "CounterHTOff": "0,1,2,3,4,5,6,7",
233 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
238 "BriefDescription": "L2 prefetch requests that hit L2 cache",
239 "Counter": "0,1,2,3",
240 "CounterHTOff": "0,1,2,3,4,5,6,7",
243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
248 "BriefDescription": "L2 prefetch requests that miss L2 cache",
249 "Counter": "0,1,2,3",
250 "CounterHTOff": "0,1,2,3,4,5,6,7",
253 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
258 "BriefDescription": "All requests that miss L2 cache",
259 "Counter": "0,1,2,3",
260 "CounterHTOff": "0,1,2,3,4,5,6,7",
264 "PublicDescription": "All requests that missed L2.",
269 "BriefDescription": "All L2 requests",
270 "Counter": "0,1,2,3",
271 "CounterHTOff": "0,1,2,3,4,5,6,7",
275 "PublicDescription": "All requests to L2 cache.",
280 "BriefDescription": "RFO requests that hit L2 cache",
281 "Counter": "0,1,2,3",
282 "CounterHTOff": "0,1,2,3,4,5,6,7",
285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
290 "BriefDescription": "RFO requests that miss L2 cache",
291 "Counter": "0,1,2,3",
292 "CounterHTOff": "0,1,2,3,4,5,6,7",
295 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
300 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
301 "Counter": "0,1,2,3",
302 "CounterHTOff": "0,1,2,3,4,5,6,7",
305 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
310 "BriefDescription": "Transactions accessing L2 pipe",
311 "Counter": "0,1,2,3",
312 "CounterHTOff": "0,1,2,3,4,5,6,7",
315 "PublicDescription": "Transactions accessing L2 pipe.",
320 "BriefDescription": "L2 cache accesses when fetching instructions",
321 "Counter": "0,1,2,3",
322 "CounterHTOff": "0,1,2,3,4,5,6,7",
325 "PublicDescription": "L2 cache accesses when fetching instructions.",
330 "BriefDescription": "Demand Data Read requests that access L2 cache",
331 "Counter": "0,1,2,3",
332 "CounterHTOff": "0,1,2,3,4,5,6,7",
335 "PublicDescription": "Demand data read requests that access L2 cache.",
340 "BriefDescription": "L1D writebacks that access L2 cache",
341 "Counter": "0,1,2,3",
342 "CounterHTOff": "0,1,2,3,4,5,6,7",
345 "PublicDescription": "L1D writebacks that access L2 cache.",
350 "BriefDescription": "L2 fill requests that access L2 cache",
351 "Counter": "0,1,2,3",
352 "CounterHTOff": "0,1,2,3,4,5,6,7",
355 "PublicDescription": "L2 fill requests that access L2 cache.",
360 "BriefDescription": "L2 writebacks that access L2 cache",
361 "Counter": "0,1,2,3",
362 "CounterHTOff": "0,1,2,3,4,5,6,7",
365 "PublicDescription": "L2 writebacks that access L2 cache.",
370 "BriefDescription": "RFO requests that access L2 cache",
371 "Counter": "0,1,2,3",
372 "CounterHTOff": "0,1,2,3,4,5,6,7",
375 "PublicDescription": "RFO requests that access L2 cache.",
381 "Counter": "0,1,2,3",
382 "CounterHTOff": "0,1,2,3,4,5,6,7",
390 "BriefDescription": "Core-originated cacheable demand requests missed L3",
391 "Counter": "0,1,2,3",
392 "CounterHTOff": "0,1,2,3,4,5,6,7",
400 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
401 "Counter": "0,1,2,3",
402 "CounterHTOff": "0,1,2,3,4,5,6,7",
410 …ription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core c…
411 "Counter": "0,1,2,3",
412 "CounterHTOff": "0,1,2,3",
413 "Data_LA": "1",
417 "PEBS": "1",
423 "Counter": "0,1,2,3",
424 "CounterHTOff": "0,1,2,3",
425 "Data_LA": "1",
429 "PEBS": "1",
434 …on": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core …
435 "Counter": "0,1,2,3",
436 "CounterHTOff": "0,1,2,3",
437 "Data_LA": "1",
441 "PEBS": "1",
447 "Counter": "0,1,2,3",
448 "CounterHTOff": "0,1,2,3",
449 "Data_LA": "1",
453 "PEBS": "1",
459 "Counter": "0,1,2,3",
460 "CounterHTOff": "0,1,2,3",
461 "Data_LA": "1",
465 "PEBS": "1",
472 "Counter": "0,1,2,3",
473 "CounterHTOff": "0,1,2,3",
474 "Data_LA": "1",
478 "PEBS": "1",
484 "Counter": "0,1,2,3",
485 "CounterHTOff": "0,1,2,3",
486 "Data_LA": "1",
490 "PEBS": "1",
496 "Counter": "0,1,2,3",
497 "CounterHTOff": "0,1,2,3",
498 "Data_LA": "1",
502 "PEBS": "1",
508 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
509 "Counter": "0,1,2,3",
510 "CounterHTOff": "0,1,2,3",
511 "Data_LA": "1",
515 "PEBS": "1",
520 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
521 "Counter": "0,1,2,3",
522 "CounterHTOff": "0,1,2,3",
523 "Data_LA": "1",
527 "PEBS": "1",
528 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
534 "Counter": "0,1,2,3",
535 "CounterHTOff": "0,1,2,3",
536 "Data_LA": "1",
540 "PEBS": "1",
546 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
547 "Counter": "0,1,2,3",
548 "CounterHTOff": "0,1,2,3",
549 "Data_LA": "1",
553 "PEBS": "1",
560 "Counter": "0,1,2,3",
561 "CounterHTOff": "0,1,2,3",
562 "Data_LA": "1",
566 "PEBS": "1",
572 "Counter": "0,1,2,3",
573 "CounterHTOff": "0,1,2,3",
574 "Data_LA": "1",
578 "L1_Hit_Indication": "1",
579 "PEBS": "1",
585 "Counter": "0,1,2,3",
586 "CounterHTOff": "0,1,2,3",
587 "Data_LA": "1",
591 "PEBS": "1",
597 "Counter": "0,1,2,3",
598 "CounterHTOff": "0,1,2,3",
599 "Data_LA": "1",
603 "PEBS": "1",
609 "Counter": "0,1,2,3",
610 "CounterHTOff": "0,1,2,3",
611 "Data_LA": "1",
615 "L1_Hit_Indication": "1",
616 "PEBS": "1",
622 "Counter": "0,1,2,3",
623 "CounterHTOff": "0,1,2,3",
624 "Data_LA": "1",
628 "PEBS": "1",
634 "Counter": "0,1,2,3",
635 "CounterHTOff": "0,1,2,3",
636 "Data_LA": "1",
640 "L1_Hit_Indication": "1",
641 "PEBS": "1",
647 "Counter": "0,1,2,3",
648 "CounterHTOff": "0,1,2,3,4,5,6,7",
657 "Counter": "0,1,2,3",
658 "CounterHTOff": "0,1,2,3,4,5,6,7",
667 "Counter": "0,1,2,3",
668 "CounterHTOff": "0,1,2,3,4,5,6,7",
678 "Counter": "0,1,2,3",
679 "CounterHTOff": "0,1,2,3,4,5,6,7",
688 "Counter": "0,1,2,3",
689 "CounterHTOff": "0,1,2,3,4,5,6,7",
697 "Counter": "0,1,2,3",
698 "CounterHTOff": "0,1,2,3,4,5,6,7",
702 …ffcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
708 "Counter": "0,1,2,3",
709 "CounterHTOff": "0,1,2,3,4,5,6,7",
710 "CounterMask": "1",
719 "Counter": "0,1,2,3",
720 "CounterHTOff": "0,1,2,3,4,5,6,7",
721 "CounterMask": "1",
730 "Counter": "0,1,2,3",
731 "CounterHTOff": "0,1,2,3,4,5,6,7",
732 "CounterMask": "1",
741 "Counter": "0,1,2,3",
742 "CounterHTOff": "0,1,2,3,4,5,6,7",
746 … "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
752 "Counter": "0,1,2,3",
753 "CounterHTOff": "0,1,2,3,4,5,6,7",
757 … "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
763 "Counter": "0,1,2,3",
764 "CounterHTOff": "0,1,2,3,4,5,6,7",
774 "Counter": "0,1,2,3",
775 "CounterHTOff": "0,1,2,3,4,5,6,7",
779 …ption": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
785 "Counter": "0,1,2,3",
786 "CounterHTOff": "0,1,2,3",
794 "Counter": "0,1,2,3",
795 "CounterHTOff": "0,1,2,3",
800 "Offcore": "1",
807 "Counter": "0,1,2,3",
808 "CounterHTOff": "0,1,2,3",
813 "Offcore": "1",
820 "Counter": "0,1,2,3",
821 "CounterHTOff": "0,1,2,3",
826 "Offcore": "1",
833 "Counter": "0,1,2,3",
834 "CounterHTOff": "0,1,2,3",
839 "Offcore": "1",
846 "Counter": "0,1,2,3",
847 "CounterHTOff": "0,1,2,3",
852 "Offcore": "1",
859 "Counter": "0,1,2,3",
860 "CounterHTOff": "0,1,2,3",
865 "Offcore": "1",
872 "Counter": "0,1,2,3",
873 "CounterHTOff": "0,1,2,3",
878 "Offcore": "1",
885 "Counter": "0,1,2,3",
886 "CounterHTOff": "0,1,2,3",
891 "Offcore": "1",
898 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3",
904 "Offcore": "1",
911 "Counter": "0,1,2,3",
912 "CounterHTOff": "0,1,2,3",
917 "Offcore": "1",
924 "Counter": "0,1,2,3",
925 "CounterHTOff": "0,1,2,3",
930 "Offcore": "1",
937 "Counter": "0,1,2,3",
938 "CounterHTOff": "0,1,2,3",
943 "Offcore": "1",
950 "Counter": "0,1,2,3",
951 "CounterHTOff": "0,1,2,3",
956 "Offcore": "1",
963 "Counter": "0,1,2,3",
964 "CounterHTOff": "0,1,2,3",
969 "Offcore": "1",
976 "Counter": "0,1,2,3",
977 "CounterHTOff": "0,1,2,3",
982 "Offcore": "1",
988 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
989 "Counter": "0,1,2,3",
990 "CounterHTOff": "0,1,2,3",
995 "Offcore": "1",
996 "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
1001 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
1002 "Counter": "0,1,2,3",
1003 "CounterHTOff": "0,1,2,3",
1008 "Offcore": "1",
1009 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
1015 "Counter": "0,1,2,3",
1016 "CounterHTOff": "0,1,2,3",
1021 "Offcore": "1",
1028 "Counter": "0,1,2,3",
1029 "CounterHTOff": "0,1,2,3",
1034 "Offcore": "1",
1041 "Counter": "0,1,2,3",
1042 "CounterHTOff": "0,1,2,3",
1047 "Offcore": "1",
1054 "Counter": "0,1,2,3",
1055 "CounterHTOff": "0,1,2,3,4,5,6,7",