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/linux/drivers/w1/masters/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire bus master configuration
6 menu "1-wire Bus Masters"
9 tristate "AMD AXI 1-wire bus host"
11 Say Y here is you want to support the AMD AXI 1-wire IP core.
13 correctly timed 1 wire transactions without relying on GPIO timing
20 tristate "Matrox G400 transport layer for 1-wire"
23 Say Y here if you want to communicate with your 1-wire devices
30 tristate "DS2490 USB <-> W1 transport layer for 1-wire"
33 Say Y here if you want to have a driver for DS2490 based USB <-> W1 bridges,
[all …]
H A Damd_axi_w1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver
5 * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
23 /* 1-wire AMD IP definition */
68 * amd_axi_w1_wait_irq_interruptible_timeout() - Wait for IRQ with timeout.
73 * Return: %0 - OK, %-EINTR - Interrupted, %-EBUSY - Timed out
81 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_wait_irq_interruptible_timeout()
82 ret = wait_event_interruptible_timeout(amd_axi_w1_local->wait_queue, in amd_axi_w1_wait_irq_interruptible_timeout()
83 atomic_read(&amd_axi_w1_local->flag) != 0, in amd_axi_w1_wait_irq_interruptible_timeout()
86 dev_err(amd_axi_w1_local->dev, "Wait IRQ Interrupted\n"); in amd_axi_w1_wait_irq_interruptible_timeout()
[all …]
H A Dsgi_w1.c1 // SPDX-License-Identifier: GPL-2.0
3 * sgi_w1.c - w1 master driver for one wire support in SGI ASICs
13 #include <linux/platform_data/sgi-w1.h>
18 #define MCR_DONE BIT(1)
36 return (mcr_val & MCR_RD_DATA) ? 1 : 0; in sgi_w1_wait()
41 * reset the device on the One Wire interface
49 writel(MCR_PACK(520, 65), dev->mcr); in sgi_w1_reset_bus()
50 ret = sgi_w1_wait(dev->mcr); in sgi_w1_reset_bus()
56 * this is the low level routine to read/write a bit on the One Wire
58 * to 0, otherwise a write 1/read.
[all …]
/linux/drivers/w1/slaves/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire slaves configuration
6 menu "1-wire Slaves"
11 Say Y here if you want to connect 1-wire thermal sensors to your
12 wire.
17 Say Y here if you want to connect 1-wire
18 simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire.
23 Say Y or M here if you want to use a DS2405 1-wire
24 single-channel addressable switch.
25 This device can also work as a single-channel
[all …]
/linux/Documentation/w1/masters/
H A Dw1-uart.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …ng a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
[all …]
H A Domap-hdq.rst2 Kernel driver for omap HDQ/1-wire module
7 HDQ/1-wire controller on the TI OMAP 2430/3430 platforms.
15 The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware
17 Semiconductor 1-Wire protocols. These protocols use a single wire for
18 communication between the master (HDQ/1-Wire controller) and the slave
19 (HDQ/1-Wire external compliant device).
21 A typical application of the HDQ/1-Wire module is the communication with battery
24 The controller supports operation in both HDQ and 1-wire mode. The essential
25 difference between the HDQ and 1-wire mode is how the slave device responds to
29 does not respond with a presence pulse as it does in the 1-Wire protocol.
[all …]
/linux/Documentation/devicetree/bindings/w1/
H A Dw1-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
[all …]
H A Damd,axi-1wire-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
10 - Kris Chaplin <kris.chaplin@amd.com>
14 const: amd,axi-1wire-host
17 maxItems: 1
20 maxItems: 1
23 maxItems: 1
[all …]
/linux/include/linux/mfd/
H A Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
18 #define CPCAP_VENDOR_TI 1
20 #define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1)
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
33 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
37 #define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */
41 #define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */
47 #define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
50 #define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */
[all …]
/linux/Documentation/peci/
H A Dpeci.rst1 .. SPDX-License-Identifier: GPL-2.0-only
13 controller is acting as a PECI originator and the processor - as
15 PECI can be used in both single processor and multiple-processor based
24 PECI Wire
25 ---------
27 PECI Wire interface uses a single wire for self-clocking and data
28 transfer. It does not require any additional control lines - the
29 physical layer is a self-clocked one-wire bus signal that begins each
32 value is logic '0' or logic '1'. PECI Wire also includes variable data
35 For PECI Wire, each processor package will utilize unique, fixed
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dintel,ce4100-lapic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
20 See [1] Chapter 8 for more details.
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
32 const: intel,ce4100-lapic
35 maxItems: 1
37 interrupt-controller: true
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dtpo,tpg110.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Thierry Reding <thierry.reding@gmail.com>
17 and other properties, and has a control interface over 3WIRE
20 self-describing.
22 +--------+
23 SPI -> | TPO | -> physical display
24 RGB -> | TPG110 |
[all …]
/linux/arch/sh/mm/
H A Dtlb-urb.c2 * arch/sh/mm/tlb-urb.c
4 * TLB entry wiring helpers for URB-equipped parts.
18 * Load the entry for 'addr' into the TLB and wire the entry.
32 * Make sure we're not trying to wire the last TLB entry slot. in tlb_wire_entry()
34 BUG_ON(!--urb); in tlb_wire_entry()
39 * Insert this entry into the highest non-wired TLB slot (via in tlb_wire_entry()
49 /* ... and wire it up. */ in tlb_wire_entry()
64 * It should also be noted that it is not possible to wire and unwire
65 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
66 * by entry N+1, you must unwire entry N+1 first, then entry N. In this
/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define PA_SDPOW (-1)
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
62 #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
63 #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
64 #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
65 #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
66 #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
75 #define PA_POFF (-1)
84 #define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Dtso.py2 # SPDX-License-Identifier: GPL-2.0
40 listen_cmd = f"socat -{ipver} -t 2 -u TCP-LISTEN:{port},reuseport /dev/null,ignoreeof"
64 # TCP falls back to non-LSO.
75 ksft_ge(qstat_new['tx-hw-gso-packets'] -
76 qstat_old['tx-hw-gso-packets'],
78 comment="Number of LSO super-packets with LSO enabled")
80 ksft_ge(qstat_new['tx-hw-gso-wire-packets'] -
81 qstat_old['tx-hw-gso-wire-packets'],
83 comment="Number of LSO wire-packets with LSO enabled")
86 ksft_lt(qstat_new['tx-hw-gso-packets'] -
[all …]
/linux/Documentation/iio/
H A Dad4000.rst1 .. SPDX-License-Identifier: GPL-2.0-only
41 * `AD7988-1 <https://www.analog.com/AD7988-1>`_
42 * `AD7988-5 <https://www.analog.com/AD7988-5>`_
45 ------------------
50 CS mode, 3-wire turbo mode
53 Datasheet "3-wire" mode is what most resembles standard SPI connection which,
56 "CS Mode, 3-Wire Turbo Mode" connection in datasheets.
57 NOTE: The datasheet definition of 3-wire mode for the AD4000 series is NOT the
58 same of standard spi-3wire mode.
62 Omit the ``adi,sdi-pin`` property in device tree to select this mode.
[all …]
/linux/sound/ppc/
H A Dsnd_ps3_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * three wire serial
49 * n:0..1
66 can be cleared by writing a '1' to the corresponding bit. A new interrupt
73 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
75 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
77 #define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2))
86 #define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1)
96 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
98 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
[all …]
/linux/drivers/w1/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Dallas's 1-wire support"
6 Dallas' 1-wire bus is useful to connect slow 1-pin devices
12 will be called wire.
22 information see <file:Documentation/driver-api/connector.rst>.
24 1. Events. They are generated each time new master or slave device found
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
3 # Makefile for the Dallas's 1-wire bus.
6 obj-$(CONFIG_W1) += wire.o
7 wire-objs := w1.o w1_int.o w1_family.o w1_netlink.o w1_io.o
9 obj-y += masters/ slaves/
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dti,am3359-tsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: ti,am3359-tsc
17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen
22 ti,x-plate-resistance:
26 ti,coordinate-readouts:
33 minimum: 1
[all …]
/linux/include/linux/platform_data/
H A Dusb-omap1.h15 * - "A" connector (rectagular)
17 * - "B" connector (squarish) or "Mini-B"
19 * - "Mini-AB" connector (very similar to Mini-B)
22 unsigned register_host:1;
23 unsigned register_dev:1;
24 u8 otg; /* port number, 1-based: usb1 == 2 */
35 * 2 == usb0-only, using internal transceiver
36 * 3 == 3 wire bidirectional
37 * 4 == 4 wire bidirectional
38 * 6 == 6 wire unidirectional (or TLL)
/linux/drivers/base/regmap/
H A Dregmap-w1.c1 // SPDX-License-Identifier: GPL-2.0
3 // Register map access API - W1 (1-Wire) support
18 * 1-Wire slaves registers with addess 8 bit and data 8 bit
28 return -EINVAL; in w1_reg_a8_v8_read()
30 mutex_lock(&sl->master->bus_mutex); in w1_reg_a8_v8_read()
32 w1_write_8(sl->master, W1_CMD_READ_DATA); in w1_reg_a8_v8_read()
33 w1_write_8(sl->master, reg); in w1_reg_a8_v8_read()
34 *val = w1_read_8(sl->master); in w1_reg_a8_v8_read()
36 ret = -ENODEV; in w1_reg_a8_v8_read()
38 mutex_unlock(&sl->master->bus_mutex); in w1_reg_a8_v8_read()
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
23 - There can be only one slave device.
25 - The spi slave node should claim the following flags which are
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dawinic,aw8738.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
14 (set using one-wire pulse control). The mode configures the speaker-guard
18 - $ref: dai-common.yaml#
24 mode-gpios:
26 GPIO used for one-wire pulse control. The pin is typically called SHDN
27 (active-low), but this is misleading since it is actually more than
29 maxItems: 1
[all …]
/linux/include/linux/
H A Dw1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * struct w1_reg_num - broken out slave device id
49 * struct w1_slave - holds a single slave device on the bus
51 * @owner: Points to the one wire "wire" kernel module.
84 * struct w1_bus_master - operations available on a bus master
89 * @return the level read (0 or 1)
93 * @touch_bit: the lowest-level function for devices that really support the
94 * 1-wire protocol.
95 * touch_bit(0) = write-0 cycle
96 * touch_bit(1) = write-1 / read cycle
[all …]

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