Searched +full:0 +full:xfffffe50 (Results 1 – 7 of 7) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | atmel,at91sam9x5-sckc.yaml | 31 enum: [0, 1] 57 const: 0 65 reg = <0xfffffe50 0x4>;
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H A D | at91-clock.txt | 16 - #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. 26 reg = <0xfffffe50 0x4>; 28 #clock-cells = <0>; 53 reg = <0xf0018000 0x120>;
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/freebsd/sys/contrib/device-tree/src/arm/microchip/ |
H A D | at91sam9n12.dtsi | 42 #size-cells = <0>; 44 cpu@0 { 47 reg = <0>; 53 reg = <0x20000000 0x10000000>; 59 #clock-cells = <0>; 60 clock-frequency = <0>; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 72 reg = <0x00300000 0x8000>; 75 ranges = <0 0x00300000 0x8000>; [all …]
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H A D | at91sam9x5.dtsi | 44 #size-cells = <0>; 46 cpu@0 { 49 reg = <0>; 55 reg = <0x20000000 0x10000000>; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 67 #clock-cells = <0>; 68 clock-frequency = <0>; 73 #clock-cells = <0>; [all...] |
H A D | sama5d3.dtsi | 46 #size-cells = <0>; 47 cpu@0 { 50 reg = <0x0>; 56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; 61 reg = <0x20000000 0x8000000>; 67 #clock-cells = <0>; 68 clock-frequency = <0>; 73 #clock-cells = <0>; 74 clock-frequency = <0>; [all...] |
H A D | sam9x60.dtsi | 37 #size-cells = <0>; 39 cpu@0 { 42 reg = <0>; 48 reg = <0x20000000 0x10000000>; 54 #clock-cells = <0>; 59 #clock-cells = <0>; 65 reg = <0x00300000 0x100000>; 68 ranges = <0 0x00300000 0x100000>; 79 #size-cells = <0>; 81 reg = <0x00500000 0x100000 [all …]
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/freebsd/sys/dev/qlnx/qlnxe/ |
H A D | ecore_init_values.h | 35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */ 36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */ 37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */ 38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */ 40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */ 41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */ 42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */ 43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */ 44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */ 45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */ [all …]
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