Lines Matching +full:0 +full:xfffffe50
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
93 reg = <0x00600000 0x100000>;
102 reg = <0x00700000 0x100000>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
167 reg = <0xf0000000 0x200>;
171 ranges = <0x0 0xf0000000 0x800>;
176 reg = <0x200 0x200>;
179 (AT91_XDMAC_DT_MEM_IF(0) |
183 (AT91_XDMAC_DT_MEM_IF(0) |
197 reg = <0x400 0x200>;
202 (AT91_XDMAC_DT_MEM_IF(0) |
206 (AT91_XDMAC_DT_MEM_IF(0) |
216 reg = <0x600 0x200>;
220 (AT91_XDMAC_DT_MEM_IF(0) |
224 (AT91_XDMAC_DT_MEM_IF(0) |
235 reg = <0xf0004000 0x200>;
239 ranges = <0x0 0xf0004000 0x800>;
244 reg = <0x200 0x200>;
248 (AT91_XDMAC_DT_MEM_IF(0) |
252 (AT91_XDMAC_DT_MEM_IF(0) |
266 reg = <0x400 0x200>;
271 (AT91_XDMAC_DT_MEM_IF(0) |
275 (AT91_XDMAC_DT_MEM_IF(0) |
285 reg = <0x600 0x200>;
289 (AT91_XDMAC_DT_MEM_IF(0) |
293 (AT91_XDMAC_DT_MEM_IF(0) |
304 reg = <0xf0008000 0x1000>;
305 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
313 reg = <0xf0010000 0x4000>;
316 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
319 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
329 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
333 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
336 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
343 #size-cells = <0>;
349 reg = <0xf001c000 0x100>;
352 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
355 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
365 reg = <0xf0020000 0x200>;
369 ranges = <0x0 0xf0020000 0x800>;
374 reg = <0x200 0x200>;
377 (AT91_XDMAC_DT_MEM_IF(0) |
381 (AT91_XDMAC_DT_MEM_IF(0) |
395 reg = <0x600 0x200>;
399 (AT91_XDMAC_DT_MEM_IF(0) |
403 (AT91_XDMAC_DT_MEM_IF(0) |
414 reg = <0xf0024000 0x200>;
418 ranges = <0x0 0xf0024000 0x800>;
423 reg = <0x200 0x200>;
426 (AT91_XDMAC_DT_MEM_IF(0) |
430 (AT91_XDMAC_DT_MEM_IF(0) |
444 reg = <0x600 0x200>;
448 (AT91_XDMAC_DT_MEM_IF(0) |
452 (AT91_XDMAC_DT_MEM_IF(0) |
463 reg = <0xf0028000 0x100>;
471 reg = <0xf002c000 0x100>;
472 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
474 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
483 reg = <0xf0030000 0x100>;
484 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
490 reg = <0xf0034000 0x100>;
491 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
493 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
496 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
505 reg = <0xf0038000 0x100>;
506 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
520 reg = <0xf003c000 0x100>;
523 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
533 reg = <0xf8000000 0x300>;
542 reg = <0xf8004000 0x300>;
552 #size-cells = <0>;
553 reg = <0xf8008000 0x100>;
554 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
555 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
562 #size-cells = <0>;
563 reg = <0xf800c000 0x100>;
564 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
565 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
571 reg = <0xf8010000 0x200>;
575 ranges = <0x0 0xf8010000 0x800>;
580 reg = <0x200 0x200>;
583 (AT91_XDMAC_DT_MEM_IF(0) |
587 (AT91_XDMAC_DT_MEM_IF(0) |
601 reg = <0x600 0x200>;
605 (AT91_XDMAC_DT_MEM_IF(0) |
609 (AT91_XDMAC_DT_MEM_IF(0) |
620 reg = <0xf8014000 0x200>;
624 ranges = <0x0 0xf8014000 0x800>;
629 reg = <0x200 0x200>;
632 (AT91_XDMAC_DT_MEM_IF(0) |
636 (AT91_XDMAC_DT_MEM_IF(0) |
650 reg = <0x600 0x200>;
654 (AT91_XDMAC_DT_MEM_IF(0) |
658 (AT91_XDMAC_DT_MEM_IF(0) |
669 reg = <0xf8018000 0x200>;
673 ranges = <0x0 0xf8018000 0x800>;
678 reg = <0x200 0x200>;
681 (AT91_XDMAC_DT_MEM_IF(0) |
685 (AT91_XDMAC_DT_MEM_IF(0) |
699 reg = <0x600 0x200>;
703 (AT91_XDMAC_DT_MEM_IF(0) |
707 (AT91_XDMAC_DT_MEM_IF(0) |
718 reg = <0xf801c000 0x200>;
722 ranges = <0x0 0xf801c000 0x800>;
727 reg = <0x200 0x200>;
730 (AT91_XDMAC_DT_MEM_IF(0) |
732 AT91_XDMAC_DT_PERID(0))>,
734 (AT91_XDMAC_DT_MEM_IF(0) |
748 reg = <0x400 0x200>;
753 (AT91_XDMAC_DT_MEM_IF(0) |
755 AT91_XDMAC_DT_PERID(0))>,
757 (AT91_XDMAC_DT_MEM_IF(0) |
767 reg = <0x600 0x200>;
771 (AT91_XDMAC_DT_MEM_IF(0) |
773 AT91_XDMAC_DT_PERID(0))>,
775 (AT91_XDMAC_DT_MEM_IF(0) |
786 reg = <0xf8020000 0x200>;
790 ranges = <0x0 0xf8020000 0x800>;
795 reg = <0x200 0x200>;
798 (AT91_XDMAC_DT_MEM_IF(0) |
802 (AT91_XDMAC_DT_MEM_IF(0) |
816 reg = <0x400 0x200>;
821 (AT91_XDMAC_DT_MEM_IF(0) |
825 (AT91_XDMAC_DT_MEM_IF(0) |
835 reg = <0x600 0x200>;
839 (AT91_XDMAC_DT_MEM_IF(0) |
843 (AT91_XDMAC_DT_MEM_IF(0) |
854 reg = <0xf8024000 0x200>;
858 ranges = <0x0 0xf8024000 0x800>;
863 reg = <0x200 0x200>;
866 (AT91_XDMAC_DT_MEM_IF(0) |
870 (AT91_XDMAC_DT_MEM_IF(0) |
884 reg = <0x400 0x200>;
889 (AT91_XDMAC_DT_MEM_IF(0) |
893 (AT91_XDMAC_DT_MEM_IF(0) |
903 reg = <0x600 0x200>;
907 (AT91_XDMAC_DT_MEM_IF(0) |
911 (AT91_XDMAC_DT_MEM_IF(0) |
922 reg = <0xf8028000 0x200>;
926 ranges = <0x0 0xf8028000 0x800>;
931 reg = <0x200 0x200>;
934 (AT91_XDMAC_DT_MEM_IF(0) |
938 (AT91_XDMAC_DT_MEM_IF(0) |
952 reg = <0x400 0x200>;
957 (AT91_XDMAC_DT_MEM_IF(0) |
961 (AT91_XDMAC_DT_MEM_IF(0) |
971 reg = <0x600 0x200>;
975 (AT91_XDMAC_DT_MEM_IF(0) |
979 (AT91_XDMAC_DT_MEM_IF(0) |
990 reg = <0xf802c000 0x1000>;
999 reg = <0xf8030000 0x1000>;
1008 reg = <0xf8034000 0x300>;
1017 reg = <0xf8038000 0x4000>;
1018 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1028 #size-cells = <0>;
1030 port@0 {
1032 #size-cells = <0>;
1033 reg = <0>;
1045 reg = <0xf8040000 0x200>;
1049 ranges = <0x0 0xf8040000 0x800>;
1054 reg = <0x200 0x200>;
1057 (AT91_XDMAC_DT_MEM_IF(0) |
1061 (AT91_XDMAC_DT_MEM_IF(0) |
1075 reg = <0x600 0x200>;
1079 (AT91_XDMAC_DT_MEM_IF(0) |
1083 (AT91_XDMAC_DT_MEM_IF(0) |
1094 reg = <0xf8044000 0x200>;
1098 ranges = <0x0 0xf8044000 0x800>;
1103 reg = <0x200 0x200>;
1106 (AT91_XDMAC_DT_MEM_IF(0) |
1110 (AT91_XDMAC_DT_MEM_IF(0) |
1124 reg = <0x600 0x200>;
1128 (AT91_XDMAC_DT_MEM_IF(0) |
1132 (AT91_XDMAC_DT_MEM_IF(0) |
1143 reg = <0xf8048000 0x100>;
1150 #size-cells = <0>;
1156 reg = <0xf804c000 0x100>;
1160 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1172 reg = <0xf8050000 0x100>;
1177 reg = <0xffffde00 0x200>;
1182 reg = <0xffffe000 0x300>,
1183 <0xffffe600 0x100>;
1188 reg = <0xffffe800 0x200>;
1195 reg = <0xffffea00 0x100>;
1202 reg = <0xfffff100 0x100>;
1208 reg = <0xfffff200 0x200>;
1212 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1215 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1227 ranges = <0xfffff400 0xfffff400 0x800>;
1232 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1233 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1234 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1235 0x003fffff 0x003f8000 0x00000000 /* pioD */
1240 reg = <0xfffff400 0x200>;
1251 reg = <0xfffff600 0x200>;
1263 reg = <0xfffff800 0x200>;
1274 reg = <0xfffffa00 0x200>;
1287 reg = <0xfffffc00 0x200>;
1290 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1296 reg = <0xfffffe00 0x10>;
1297 clocks = <&clk32k 0>;
1302 reg = <0xfffffe10 0x10>;
1303 clocks = <&clk32k 0>;
1305 #size-cells = <0>;
1313 reg = <0xfffffe20 0x20>;
1315 clocks = <&clk32k 0>;
1320 reg = <0xfffffe40 0x10>;
1327 reg = <0xfffffe50 0x4>;
1334 reg = <0xfffffe60 0x10>;
1339 reg = <0xfffffea8 0x100>;
1341 clocks = <&clk32k 0>;
1346 reg = <0xffffff80 0x24>;
1348 clocks = <&clk32k 0>;