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Searched +full:0 +full:xfffff000 (Results 1 – 25 of 160) sorted by relevance

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/linux/drivers/video/fbdev/via/
H A Daccel.c19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
35 return 0; in viafb_set_bpp()
44 u32 ge_cmd = 0, tmp, i; in hw_bitblt_1()
54 ge_cmd |= 0x00008000; in hw_bitblt_1()
59 ge_cmd |= 0x00004000; in hw_bitblt_1()
67 case 0x00: /* blackness */ in hw_bitblt_1()
68 case 0x5A: /* pattern inversion */ in hw_bitblt_1()
69 case 0xF0: /* pattern copy */ in hw_bitblt_1()
70 case 0xFF: /* whiteness */ in hw_bitblt_1()
84 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000) in hw_bitblt_1()
[all …]
/linux/drivers/bcma/
H A Dscan.h5 #define BCMA_ADDR_BASE 0x18000000
6 #define BCMA_WRAP_BASE 0x18100000
8 #define SCAN_ER_VALID 0x00000001
9 #define SCAN_ER_TAGX 0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADD…
10 #define SCAN_ER_TAG 0x0000000E
11 #define SCAN_ER_TAG_CI 0x00000000
12 #define SCAN_ER_TAG_MP 0x00000002
13 #define SCAN_ER_TAG_ADDR 0x00000004
14 #define SCAN_ER_TAG_END 0x0000000E
15 #define SCAN_ER_BAD 0xFFFFFFFF
[all …]
/linux/arch/arm/mach-s3c/
H A Dcpu.h19 #define S3C6400_CPU_ID 0x36400000
20 #define S3C6410_CPU_ID 0x36410000
21 #define S3C64XX_CPU_MASK 0xFFFFF000
23 #define S5PV210_CPU_ID 0x43110000
24 #define S5PV210_CPU_MASK 0xFFFFF000
40 # define soc_is_s3c6400() 0
41 # define soc_is_s3c6410() 0
42 # define soc_is_s3c64xx() 0
/linux/arch/powerpc/include/asm/nohash/32/
H A Dmmu-8xx.h16 #define MI_GPM 0x80000000 /* Set domain manager mode */
17 #define MI_PPM 0x40000000 /* Set subpage protection */
18 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
20 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
24 * Ks = 0, Kp = 1.
27 #define MI_Ks 0x80000000 /* Should not be set */
28 #define MI_Kp 0x40000000 /* Should always be set */
39 * 0 => Kernel => 11 (all accesses performed according as user iaw page definition)
[all …]
H A Dmmu-44x.h10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
13 #define PPC44x_TLB_PAGEID 0
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
[all …]
/linux/samples/bpf/
H A Dtcp_rwnd_kern.c53 if (skops->local_ip6[0] != skops->remote_ip6[0] || in bpf_rwnd()
54 (bpf_ntohl(skops->local_ip6[1]) & 0xfffff000) != in bpf_rwnd()
55 (bpf_ntohl(skops->remote_ip6[1]) & 0xfffff000)) in bpf_rwnd()
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_global_conf_masks.h24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
25 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
29 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
33 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10
37 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20
39 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40
41 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dgt215.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_dma */
6 /* 0x0004: ctx_dma_query */
7 0x00000000,
8 /* 0x0008: ctx_dma_src */
9 0x00000000,
10 /* 0x000c: ctx_dma_dst */
11 0x00000000,
12 /* 0x0010: ctx_query_address_high */
[all …]
H A Dgf100.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_query_address_high */
6 0x00000000,
7 /* 0x0008: ctx_query_address_low */
8 0x00000000,
9 /* 0x000c: ctx_query_counter */
10 0x00000000,
11 /* 0x0010: ctx_src_address_high */
12 0x00000000,
[all …]
/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux/arch/hexagon/include/asm/
H A Dvm_mmu.h24 #define __HVM_PDE_S (0x7 << 0)
25 #define __HVM_PDE_S_4KB 0
35 #define __HVM_PDE_PTMASK_4KB 0xfffff000
36 #define __HVM_PDE_PTMASK_16KB 0xfffffc00
37 #define __HVM_PDE_PTMASK_64KB 0xffffff00
38 #define __HVM_PDE_PTMASK_256KB 0xffffffc0
39 #define __HVM_PDE_PTMASK_1MB 0xfffffff0
46 #define __HVM_PTE_C (0x7<<6)
56 #define __HEXAGON_C_WB 0x0 /* Write-back, no L2 */
57 #define __HEXAGON_C_WT 0x1 /* Write-through, no L2 */
[all …]
/linux/arch/riscv/kernel/
H A Dmodule.c58 u32 insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16; in riscv_insn_rmw()
63 parcel[0] = cpu_to_le16(insn); in riscv_insn_rmw()
65 return 0; in riscv_insn_rmw()
77 return 0; in riscv_insn_rvc_rmw()
88 return 0; in apply_r_riscv_32_rela()
94 return 0; in apply_r_riscv_64_rela()
101 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
102 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
103 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
104 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
[all …]
/linux/arch/x86/kernel/
H A Drelocate_kernel_32.S28 #define ESP DATA(0x0)
29 #define CR0 DATA(0x4)
30 #define CR3 DATA(0x8)
31 #define CR4 DATA(0xc)
34 #define CP_VA_CONTROL_PAGE DATA(0x10)
35 #define CP_PA_PGD DATA(0x14)
36 #define CP_PA_SWAP_PAGE DATA(0x18)
37 #define CP_PA_BACKUP_PAGES_MAP DATA(0x1c)
67 pushl $0
102 /* set return address to 0 if not preserving context */
[all …]
/linux/arch/arm/mach-exynos/
H A Dcommon.h14 #define EXYNOS3250_SOC_ID 0xE3472000
15 #define EXYNOS3_SOC_MASK 0xFFFFF000
17 #define EXYNOS4210_CPU_ID 0x43210000
18 #define EXYNOS4212_CPU_ID 0x43220000
19 #define EXYNOS4412_CPU_ID 0xE4412200
20 #define EXYNOS4_CPU_MASK 0xFFFE0000
22 #define EXYNOS5250_SOC_ID 0x43520000
23 #define EXYNOS5410_SOC_ID 0xE5410000
24 #define EXYNOS5420_SOC_ID 0xE5420000
25 #define EXYNOS5800_SOC_ID 0xE5422000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/dma/
H A Dusernv04.c46 u64 offset = dmaobj->base.start & 0xfffff000; in nv04_dmaobj_bind()
47 u64 adjust = dmaobj->base.start & 0x00000fff; in nv04_dmaobj_bind()
53 device->mmu->vmm->pd->pt[0]->memory; in nv04_dmaobj_bind()
58 offset &= 0xfffff000; in nv04_dmaobj_bind()
63 if (ret == 0) { in nv04_dmaobj_bind()
65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
66 nvkm_wo32(*pgpuobj, 0x04, length); in nv04_dmaobj_bind()
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
107 dmaobj->flags0 |= 0x00003000; in nv04_dmaobj_new()
[all …]
/linux/arch/arm/mm/
H A Dproc-arm740.S48 mrc p15, 0, r0, c1, c0, 0
49 bic r0, r0, #0x3f000000 @ bank/f/lock/s
50 bic r0, r0, #0x0000000c @ w-buffer/cache
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mov ip, #0
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
65 bic ip, ip, #0x0000000c @ ............wc..
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mov r0, #0
[all …]
/linux/arch/mips/kernel/
H A Dspram.c21 #define SPRAM_TAG0_ENABLE 0x00000080
22 #define SPRAM_TAG0_PA_MASK 0xfffff000
23 #define SPRAM_TAG1_SIZE_MASK 0xfffff000
115 unsigned int firstsize = 0, lastsize = 0; in probe_spram()
116 unsigned int firstpa = 0, lastpa = 0, pa = 0; in probe_spram()
[all...]
/linux/drivers/char/agp/
H A Dnvidia-agp.c17 #define NVIDIA_0_APSIZE 0x80
18 #define NVIDIA_1_WBC 0xf0
19 #define NVIDIA_2_GARTCTRL 0xd0
20 #define NVIDIA_2_APBASE 0xd8
21 #define NVIDIA_2_APLIMIT 0xdc
22 #define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
23 #define NVIDIA_3_APBASE 0x50
24 #define NVIDIA_3_APLIMIT 0x54
45 size_value &= 0x0f; in nvidia_fetch_size()
48 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { in nvidia_fetch_size()
[all …]
/linux/arch/mips/include/asm/mach-loongson2ef/cs5536/
H A Dcs5536.h20 #define CS5536_SB_MSR_BASE (0x00000000)
21 #define CS5536_GLIU_MSR_BASE (0x10000000)
22 #define CS5536_ILLEGAL_MSR_BASE (0x20000000)
23 #define CS5536_USB_MSR_BASE (0x40000000)
24 #define CS5536_IDE_MSR_BASE (0x60000000)
25 #define CS5536_DIVIL_MSR_BASE (0x80000000)
26 #define CS5536_ACC_MSR_BASE (0xa0000000)
27 #define CS5536_UNUSED_MSR_BASE (0xc0000000)
28 #define CS5536_GLCP_MSR_BASE (0xe0000000)
45 #define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-chipid.h11 #define EXYNOS_CHIPID_REG_PRO_ID 0x00
12 #define EXYNOS_REV_PART_MASK 0xf
14 #define EXYNOS_MASK 0xfffff000
16 #define EXYNOS_CHIPID_REG_PKG_ID 0x04
19 #define EXYNOS5422_IDS_MASK 0xff
21 #define EXYNOS5422_USESG_MASK 0x01
22 #define EXYNOS5422_SG_OFFSET 0
23 #define EXYNOS5422_SG_MASK 0x07
25 #define EXYNOS5422_TABLE_MASK 0x03
27 #define EXYNOS5422_SG_A_MASK 0x0f
[all …]
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9330_1p1_initvals.h27 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
28 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
29 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
30 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
31 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
32 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
33 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
34 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
35 {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
36 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
[all …]
/linux/arch/microblaze/include/asm/
H A Dfixmap.h33 * from the end of virtual memory (0xfffff000) backwards.
/linux/arch/s390/include/asm/
H A Druntime-const.h12 "0: iihf %[__ret],%[c1]\n" \
15 ".long 0b - .\n" \
18 : [c1] "i" (0x01234567UL), \
19 [c2] "i" (0x89abcdefUL)); \
28 "0: srl %[__ret],12\n" \
30 ".long 0b - .\n" \
44 } while (0)
63 insn &= 0xfffff000; in __runtime_fixup_shift()

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