Lines Matching +full:0 +full:xfffff000

18 #define NVIDIA_0_APSIZE		0x80
19 #define NVIDIA_1_WBC		0xf0
20 #define NVIDIA_2_GARTCTRL	0xd0
21 #define NVIDIA_2_APBASE		0xd8
22 #define NVIDIA_2_APLIMIT	0xdc
23 #define NVIDIA_2_ATTBASE(i)	(0xe0 + (i) * 4)
24 #define NVIDIA_3_APBASE		0x50
25 #define NVIDIA_3_APLIMIT	0x54
46 	size_value &= 0x0f;
49 	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
58 	return 0;
61 #define SYSCFG          0xC0010010
62 #define IORR_BASE0      0xC0010016
63 #define IORR_MASK0      0xC0010017
76 	for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
80 		if ((base_lo & 0xfffff000) == (base & 0xfffff000))
83 		if ((mask_lo & 0x00000800) == 0)
92     base_hi = 0x0;
93     base_lo = (base & ~0xfff) | 0x18;
94     mask_hi = 0xf;
95     mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
100     sys_lo |= 0x00100000;
103 	return 0;
128 	if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
134 	nvidia_private.pg_offset = 0;
135 	if (num_dirs == 0) {
143 	for (i = 0; i < 8; i++) {
150 	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
154 	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
164 	return 0;
174 	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
178 	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
208 	if (mask_type != 0 || type != mem->type)
211 	if (mem->page_count == 0)
212 		return 0;
227 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
237 	return 0;
248 	if (mask_type != 0 || type != mem->type)
251 	if (mem->page_count == 0)
252 		return 0;
258 	return 0;
287 	for (i = 0; i < 32 + 1; i++)
289 	for (i = 0; i < 32 + 1; i++)
296 	{512, 131072, 7, 0},
307 	{ .mask = 1, .type = 0}
347 					    PCI_DEVFN(0, 1));
351 					    PCI_DEVFN(0, 2));
355 					    PCI_DEVFN(30, 0));
370 		nvidia_private.wbc_mask = 0x00010000;
374 		nvidia_private.wbc_mask = 0x80000000;
413 	return 0;
419 	.class_mask	= ~0,
427 	.class_mask	= ~0,