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/linux/arch/powerpc/boot/dts/
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,ocmem.yaml86 "-sram@[0-9a-f]+$":
106 reg = <0xfdd00000 0x2000>,
107 <0xfec00000 0x180000>;
118 ranges = <0 0xfec00000 0x100000>;
120 gmu-sram@0 {
121 reg = <0x0 0x100000>;
/linux/arch/arm/mach-davinci/
H A Dhardware.h23 #define IO_PHYS UL(0x01c00000)
24 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
25 #define IO_SIZE 0x00400000
/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml32 - pattern: '^qcom,adreno-[0-9a-f]{8}$'
38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
44 - pattern: '^amd,imageon-200\.[0-1]$'
149 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
225 pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
252 reg = <0xfdb00000 0x10000>;
266 iommus = <&gpu_iommu 0>;
273 reg = <0xfdd00000 0x2000>,
274 <0xfec00000 0x180000>;
283 ranges = <0 0xfec00000 0x100000>;
[all …]
/linux/arch/powerpc/sysdev/
H A Dgrackle.c18 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
21 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
27 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); in grackle_set_loop_snoop()
31 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); in grackle_set_loop_snoop()
38 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); in setup_grackle()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dintel,ce4100-ioapic.yaml57 reg = <0xfec00000 0x1000>;
/linux/arch/powerpc/platforms/chrp/
H A Dgg2.h23 #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
26 #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */
27 #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */
29 #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */
30 #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */
39 #define GG2_PCI_BUSNO 0x40 /* Bus number */
40 #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */
41 #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */
[all …]
/linux/arch/x86/kvm/
H A Dioapic.h14 #define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
15 #define IOAPIC_EDGE_TRIG 0
18 #define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
19 #define IOAPIC_MEM_LENGTH 0x100
22 #define IOAPIC_REG_SELECT 0x00
23 #define IOAPIC_REG_WINDOW 0x10
26 #define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
27 #define IOAPIC_REG_VERSION 0x01
28 #define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
31 #define IOAPIC_FIXED 0x0
[all …]
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Dcdn-dp-rockchip.txt39 reg = <0x0 0xfec00000 0x0 0x100000>;
53 #size-cells = <0>;
58 #size-cells = <0>;
62 #size-cells = <0>;
63 dp_in_vopb: endpoint@0 {
64 reg = <0>;
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux/arch/x86/include/asm/
H A Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/linux/arch/arm/mach-orion5x/
H A Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/linux/arch/x86/kernel/
H A Djailhouse.c48 if (boot_cpu_data.cpuid_level < 0 || in jailhouse_cpuid_base()
50 return 0; in jailhouse_cpuid_base()
52 return hypervisor_cpuid_base("Jailhouse\0\0\0", 0); in jailhouse_cpuid_base()
62 memset(now, 0, sizeof(*now)); in jailhouse_get_wallclock()
103 register_lapic_address(0xfee00000); in jailhouse_parse_smp_config()
105 for (cpu = 0; cpu < setup_data.v1.num_cpus; cpu++) in jailhouse_parse_smp_config()
111 mp_register_ioapic(0, 0xfec00000, gsi_top, &ioapic_cfg); in jailhouse_parse_smp_config()
137 if (pcibios_last_bus < 0) in jailhouse_pci_arch_init()
138 pcibios_last_bus = 0xff; in jailhouse_pci_arch_init()
142 pci_mmconfig_add(0, 0, pcibios_last_bus, in jailhouse_pci_arch_init()
[all …]
/linux/net/ipv6/
H A Daddrconf_core.c42 st = addr->s6_addr32[0]; in __ipv6_addr_type()
47 if ((st & htonl(0xE0000000)) != htonl(0x00000000) && in __ipv6_addr_type()
48 (st & htonl(0xE0000000)) != htonl(0xE0000000)) in __ipv6_addr_type()
52 if ((st & htonl(0xFF000000)) == htonl(0xFF000000)) { in __ipv6_addr_type()
59 if ((st & htonl(0xFFC00000)) == htonl(0xFE800000)) in __ipv6_addr_type()
62 if ((st & htonl(0xFFC00000)) == htonl(0xFEC00000)) in __ipv6_addr_type()
65 if ((st & htonl(0xFE000000)) == htonl(0xFC000000)) in __ipv6_addr_type()
69 if ((addr->s6_addr32[0] | addr->s6_addr32[1]) == 0) { in __ipv6_addr_type()
70 if (addr->s6_addr32[2] == 0) { in __ipv6_addr_type()
71 if (addr->s6_addr32[3] == 0) in __ipv6_addr_type()
[all …]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
46 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
160 mboxes = <&apcs 0>;
212 reg = <0x3000000 0x100000>;
217 reg = <0x0dc00000 0x1900000>;
[all …]
H A Dqcom-msm8974.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
38 cpu0: cpu@0 {
42 reg = <0>;
108 memory@0 {
110 reg = <0x0 0x0>;
135 mboxes = <&apcs 0>;
158 reg = <0x08000000 0x5100000>;
163 reg = <0x0d100000 0x100000>;
[all …]
/linux/arch/arm/probes/
H A Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]
H A Drk3588-base.dtsi56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]