Searched +full:0 +full:xfe040000 (Results 1 – 4 of 4) sorted by relevance
13 #define PCIECR 0xFE00000814 #define PCIECR_ENBL 0x0117 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */25 #define SH7780_PCIAIR 0x11C /* Error Address Register */26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */[all …]
24 # define PCICR_ENDIANNESS 031 .start = 0x1000,35 .name = "PCI MEM 0",36 .start = 0xfd000000,37 .end = 0xfd000000 + SZ_16M - 1,41 .start = 0x10000000,42 .end = 0x10000000 + SZ_64M - 1,49 .start = 0xc0000000,50 .end = 0xc0000000 + SZ_512M - 1,59 .io_offset = 0,[all …]
11 /* PCIe bus-0(x4) on SH7786 */ // Rev1.17112 #define SH4A_PCIE_SPW_BASE 0xFE000000 /* spw config address for controller 0 */13 #define SH4A_PCIE_SPW_BASE1 0xFE200000 /* spw config address for controller 1 (Rev1.14)*/14 #define SH4A_PCIE_SPW_BASE2 0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/15 #define SH4A_PCIE_SPW_BASE_LEN 0x0008000017 #define SH4A_PCI_CNFG_BASE 0xFE040000 /* pci config address for controller 0 */18 #define SH4A_PCI_CNFG_BASE1 0xFE240000 /* pci config address for controller 1 (Rev1.14)*/19 #define SH4A_PCI_CNFG_BASE2 0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/20 #define SH4A_PCI_CNFG_BASE_LEN 0x0004000022 #define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0 /* offset to pci config_address */[all …]
50 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0 0x0>;56 clocks = <&scmi_clk 0>;59 i-cache-size = <0x8000>;62 d-cache-size = <0x8000>;71 reg = <0x0 0x100>;74 i-cache-size = <0x8000>;77 d-cache-size = <0x8000>;86 reg = <0x0 0x200>;[all …]