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/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex_n6000.dts26 reg = <0 0x80000000 0 0>;
29 soc@0 {
32 reg = <0x80000000 0x60000000>,
33 <0xf9000000 0x0010000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/soc/intel/
H A Dintel,hps-copy-engine.yaml39 reg = <0x80000000 0x60000000>,
40 <0xf9000000 0x00100000>;
44 ranges = <0x00000000 0x00000000 0xf9000000 0x0000100
[all...]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmarvell,prestera.txt21 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
23 packet-processor@0 {
25 reg = <0 0x4000000>;
45 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
46 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
73 that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:
76 ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
77 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
78 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
79 phys = <&cp0_comphy0 0>;
/freebsd/sys/contrib/device-tree/src/arc/
H A Dnsimosci.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
H A Dnsimosci_hs.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
H A Dnsimosci_hs_idu.dts18 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
34 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
56 interrupts = <0>;
65 #clock-cells = <0>;
72 reg = <0xf9000000 0x400>;
79 reg = <0xf9000400 0x14>;
87 reg = <0xf0003000 0x44>;
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_calib.c71 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r88e_iq_calib_chain()
72 rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0); in r88e_iq_calib_chain()
73 rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000); in r88e_iq_calib_chain()
74 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf); in r88e_iq_calib_chain()
75 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b); in r88e_iq_calib_chain()
76 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r88e_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r88e_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_RX_IQK, 0x81004800); in r88e_iq_calib_chain()
82 /* IQ calibration settings for chain 0. */ in r88e_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1c); in r88e_iq_calib_chain()
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_calib.c76 if (chain == 0) { /* IQ calibration for chain 0. */ in r92ce_iq_calib_chain()
77 /* IQ calibration settings for chain 0. */ in r92ce_iq_calib_chain()
78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); in r92ce_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); in r92ce_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); in r92ce_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); in r92ce_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92ce_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92ce_iq_calib_chain()
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_calib.c76 if (chain == 0) { /* IQ calibration for chain 0. */ in r92c_iq_calib_chain()
77 /* IQ calibration settings for chain 0. */ in r92c_iq_calib_chain()
78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); in r92c_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); in r92c_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92c_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92c_iq_calib_chain()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8084.dtsi21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
94 reg = <0x0 0x0>;
189 interrupts = <GIC_PPI 7 0xf04>;
195 #clock-cells = <0>;
201 #clock-cells = <0>;
208 interrupts = <GIC_PPI 2 0xf08>,
209 <GIC_PPI 3 0xf08>,
[all …]
H A Dqcom-msm8226.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
40 #size-cells = <0>;
42 CPU0: cpu@0 {
46 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
160 mboxes = <&apcs 0>;
212 reg = <0x3000000 0x100000>;
217 reg = <0x0dc00000 0x1900000>;
[all …]
H A Dqcom-msm8974.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
38 CPU0: cpu@0 {
42 reg = <0>;
108 memory@0 {
110 reg = <0x0 0x0>;
135 mboxes = <&apcs 0>;
158 reg = <0x08000000 0x5100000>;
163 reg = <0x0d100000 0x100000>;
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8994.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
70 reg = <0x0 0x2>;
78 reg = <0x0 0x3>;
86 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
29 #define GPR_OFFSET_NAME(reg) 0
31 #define FPU_OFFSET_NAME(reg) 0
32 #define EXC_OFFSET_NAME(reg) 0
33 #define DBG_OFFSET_NAME(reg) 0
34 #define DBG_OFFSET_NAME(reg) 0
36 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
61 #define No_VFP 0
77 static inline bool IsZero(uint64_t x) { return x == 0; } in IsZero()
85 if (shift == 0) in LSL()
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.c19 #define WLAN_SLOT_TIME 0x09
20 #define WLAN_RL_VAL 0x3030
21 #define WLAN_BAR_VAL 0x0201ffff
22 #define BIT_MASK_TBTT_HOLD 0x00000fff
24 #define BIT_MASK_TBTT_SETUP 0x000000ff
25 #define BIT_SHIFT_TBTT_SETUP 0
30 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
31 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x6
[all...]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) in LLDB_PLUGIN_DEFINE_ADV()
47 ::memset(&reg_info, 0, sizeof(RegisterInfo)); in LLDB_PLUGIN_DEFINE_ADV()
234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV()
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV()
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV()
287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV()
423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV()
604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
609 return 0; in CountITSize()
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]