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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dmvme7100.dts18 reg = <0x00000000 0x80000000>;
22 ranges = <0x00000000 0xf1000000 0x00100000>;
27 reg = <0x4c>;
89 reg = <0xf1005000 0x1000>;
91 ranges = <0 0 0xf8000000 0x08000000 // NOR Flash (128MB)
92 2 0 0xf2030000 0x00010000 // NAND Flash (8GB)
93 3 0 0xf2400000 0x00080000 // MRAM (512KB)
94 4 0 0xf2000000 0x00010000 // BCSR
95 5 0 0xf2010000 0x00010000>; // QUART
97 bcsr@4,0 {
[all …]
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dsbc8641d.dts20 reg = <0x00000000 0x20000000>; // 512M at 0x0
24 reg = <0xf8005000 0x1000>;
26 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
27 1 0 0xf0000000 0x00010000 // 64KB EEPROM
28 2 0 0xf1000000 0x00100000 // EPLD (1MB)
29 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
30 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
31 6 0 0xf4000000 0x00100000 // LCD display (1MB)
32 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
34 flash@0,0 {
[all …]
H A Dkmcoge4.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/freebsd/lib/msun/ld128/
H A De_powl.c40 * 1. (anything) ** 0 is 1
43 * 4. NAN ** (anything except 0) is NAN
45 * 6. +-(|x| > 1) ** -INF is +0
46 * 7. +-(|x| < 1) ** +INF is +0
49 * 10. +0 ** (+anything except 0, NAN) is +0
50 * 11. -0 ** (+anything except 0, NAN, odd integer) is +0
51 * 12. +0 ** (-anything except 0, NAN) is +INF
52 * 13. -0 ** (-anything except 0, NAN, odd integer) is +INF
53 * 14. -0 ** (odd integer) = -( +0 ** (odd integer) )
54 * 15. +INF ** (+anything except 0,NAN) is +INF
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbrcm,stb-pcie.yaml162 reg = <0x0 0x7d500000 0x9310>;
170 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
171 interrupt-map = <0 0 0
[all...]
H A Drockchip,rk3399-pcie.yaml60 const: 0
97 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
98 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
99 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
102 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
103 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
105 msi-map = <0x0 &its 0x0 0x1000>;
106 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
117 pinctrl-0 = <&pcie_clkreq>;
119 interrupt-map-mask = <0 0 0 7>;
[all …]
H A Drockchip-pcie-host.txt38 - pinctrl-0: The "default" pinctrl state
51 where N ranges from 0 to 3.
75 address. The value must be 0.
89 bus-range = <0x0 0x1>;
90 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
91 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
92 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
98 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
99 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
101 msi-map = <0x0 &its 0x0 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Daxis.txt23 reg = <0xf8000000 0x48>;
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dhisilicon,hi655x.txt19 - #clock-cells: From common clock binding; shall be set to 0
28 reg = <0x0 0xf8000000 0x0 0x1000>;
32 #clock-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dartpec6.txt30 #clock-cells = <0>;
38 reg = <0xf8000000 0x48>;
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91sam9x5_can.dtsi17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear600-evb.dts17 reg = <0 0x10000000>;
55 reg = <0xf8000000 0x800000>;
63 partition@0 {
65 reg = <0x0 0x10000>;
69 reg = <0x10000 0x50000>;
73 reg = <0x60000 0x10000>;
77 reg = <0x70000 0x10000>;
81 reg = <0x80000 0x310000>;
85 reg = <0x390000 0x0>;
H A Dspear310-evb.dts18 reg = <0 0x40000000>;
24 pinctrl-0 = <&state_default>;
102 reg = <0xf8000000 0x800000>;
105 partition@0 {
107 reg = <0x0 0x10000>;
111 reg = <0x10000 0x50000>;
115 reg = <0x60000 0x10000>;
119 reg = <0x70000 0x10000>;
123 reg = <0x80000 0x310000>;
127 reg = <0x390000 0x0>;
[all …]
H A Dspear320-evb.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
103 reg = <0xf8000000 0x800000>;
106 partition@0 {
108 reg = <0x0 0x10000>;
112 reg = <0x10000 0x50000>;
116 reg = <0x60000 0x10000>;
120 reg = <0x70000 0x10000>;
124 reg = <0x80000 0x310000>;
128 reg = <0x390000 0x0>;
[all …]
H A Dspear300-evb.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
77 cd-gpios = <&gpio1 0 0>;
88 reg = <0xf8000000 0x800000>;
91 partition@0 {
93 reg = <0x0 0x10000>;
97 reg = <0x10000 0x50000>;
101 reg = <0x60000 0x10000>;
105 reg = <0x70000 0x10000>;
109 reg = <0x80000 0x310000>;
[all …]
H A Dspear320-hmi.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
102 partition@0 {
104 reg = <0x0 0x80000>;
108 reg = <0x80000 0x140000>;
112 reg = <0x1C0000 0x40000>;
116 reg = <0x200000 0x40000>;
120 reg = <0x240000 0xC00000>;
124 reg = <0xE40000 0x0>;
131 #size-cells = <0>;
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_reg.h38 /* PL AXI buses: General Purpose Port #0, M_AXI_GP0. */
39 #define ZYNQ7_PLGP0_HWBASE 0x40000000
40 #define ZYNQ7_PLGP0_SIZE 0x40000000
43 #define ZYNQ7_PLGP1_HWBASE 0x80000000
44 #define ZYNQ7_PLGP1_SIZE 0x40000000
47 #define ZYNQ7_PSIO_HWBASE 0xE0000000
48 #define ZYNQ7_PSIO_SIZE 0x00300000
52 #define ZYNQ7_UART0_SIZE 0x1000
54 #define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000)
55 #define ZYNQ7_UART1_SIZE 0x1000
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dsbc8548.dts20 reg = <0xe0000000 0x5000>;
23 ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
24 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
25 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
26 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
27 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
30 flash@0,0 {
34 reg = <0x0 0x0 0x800000>;
37 partition@0 {
40 reg = <0x00000000 0x007a0000>;
[all …]
H A Dsbc8548-altflash.dts23 reg = <0xe0000000 0x5000>;
26 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
27 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
28 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
29 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
30 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
32 flash@0,0 {
35 reg = <0x0 0x0 0x04000000>;
39 partition@0 {
42 reg = <0x00000000 0x03f00000>;
[all …]
/freebsd/lib/msun/bsdsrc/
H A Dmathimpl.h58 SET_LOW_WORD(*_dp, _lw & 0xf8000000); in _b_trunc()
/freebsd/usr.sbin/fstyp/
H A Dapfs.c63 #define OBJECT_TYPE_MASK 0x0000ffff
64 #define OBJECT_TYPE_NX_SUPERBLOCK 0x00000001
65 #define OBJECT_TYPE_FLAGS_MASK 0xffff0000
66 #define OBJ_STORAGETYPE_MASK 0xc0000000
67 #define OBJECT_TYPE_FLAGS_DEFINED_MASK 0xf8000000
68 #define OBJ_STORAGE_VIRTUAL 0x00000000
69 #define OBJ_STORAGE_EPHEMERAL 0x80000000
70 #define OBJ_STORAGE_PHYSICAL 0x40000000
71 #define OBJ_NOHEADER 0x20000000
72 #define OBJ_ENCRYPTED 0x10000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/axis/
H A Dartpec6.dtsi55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
74 reg = <0xf8000000 0x48>;
80 psci_version = <0x84000000>;
81 cpu_on = <0x84000003>;
82 system_reset = <0x84000009>;
87 reg = <0xfaf00000 0x58>;
92 #clock-cells = <0>;
98 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_calib.c71 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r88e_iq_calib_chain()
72 rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0); in r88e_iq_calib_chain()
73 rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000); in r88e_iq_calib_chain()
74 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf); in r88e_iq_calib_chain()
75 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b); in r88e_iq_calib_chain()
76 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r88e_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r88e_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_RX_IQK, 0x81004800); in r88e_iq_calib_chain()
82 /* IQ calibration settings for chain 0. */ in r88e_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1c); in r88e_iq_calib_chain()
[all …]

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