Lines Matching +full:0 +full:xf8000000
38 /* PL AXI buses: General Purpose Port #0, M_AXI_GP0. */
39 #define ZYNQ7_PLGP0_HWBASE 0x40000000
40 #define ZYNQ7_PLGP0_SIZE 0x40000000
43 #define ZYNQ7_PLGP1_HWBASE 0x80000000
44 #define ZYNQ7_PLGP1_SIZE 0x40000000
47 #define ZYNQ7_PSIO_HWBASE 0xE0000000
48 #define ZYNQ7_PSIO_SIZE 0x00300000
52 #define ZYNQ7_UART0_SIZE 0x1000
54 #define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000)
55 #define ZYNQ7_UART1_SIZE 0x1000
58 #define ZYNQ7_SMC_HWBASE 0xE1000000
59 #define ZYNQ7_SMC_SIZE 0x05000000
62 #define ZYNQ7_PSCTL_HWBASE 0xF8000000
63 #define ZYNQ7_PSCTL_SIZE 0x01000000
66 #define ZYNQ7_SLCR_SIZE 0x1000
68 #define ZYNQ7_DEVCFG_HWBASE (ZYNQ7_PSCTL_HWBASE+0x7000)
69 #define ZYNQ7_DEVCFG_SIZE 0x1000