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/freebsd/sys/contrib/device-tree/src/arm/xen/
H A Dxenvm-4.2.dts26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
51 reg = <0 0x80000000 0 0x08000000>;
57 #address-cells = <0>;
59 reg = <0 0x2c001000 0 0x1000>,
60 <0 0x2c002000 0 0x100>;
65 interrupts = <1 13 0xf08>,
66 <1 14 0xf08>,
67 <1 11 0xf08>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Decx-2000.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Darm,arch_timer.yaml121 interrupts = <1 13 0xf08>,
122 <1 14 0xf08>,
123 <1 11 0xf08>,
124 <1 10 0xf08>;
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15-tc1.dts16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
H A Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
38 reg = <0x0>;
46 reg = <0x1>;
54 reg = <0x2>;
62 reg = <0x3>;
86 #address-cells = <0x2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhip04.dtsi22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8084.dtsi21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
94 reg = <0x0 0x0>;
189 interrupts = <GIC_PPI 7 0xf04>;
195 #clock-cells = <0>;
201 #clock-cells = <0>;
208 interrupts = <GIC_PPI 2 0xf08>,
209 <GIC_PPI 3 0xf08>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dxen.txt13 Region 0 is reserved for mapping grant table, it must be always present.
47 reg = <0 0xb0000000 0 0x20000>;
48 interrupts = <1 15 0xf08>;
50 xen,uefi-system-table = <0xXXXXXXXX>;
51 xen,uefi-mmap-start = <0xXXXXXXXX>;
52 xen,uefi-mmap-size = <0xXXXXXXXX>;
53 xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
54 xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/dev/mlx4/
H A Dcmd.h43 MLX4_CMD_SYS_EN = 0x1,
44 MLX4_CMD_SYS_DIS = 0x2,
45 MLX4_CMD_MAP_FA = 0xfff,
46 MLX4_CMD_UNMAP_FA = 0xffe,
47 MLX4_CMD_RUN_FW = 0xff6,
48 MLX4_CMD_MOD_STAT_CFG = 0x34,
49 MLX4_CMD_QUERY_DEV_CAP = 0x3,
50 MLX4_CMD_QUERY_FW = 0x4,
51 MLX4_CMD_ENABLE_LAM = 0xff8,
52 MLX4_CMD_DISABLE_LAM = 0xff7,
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1f
[all...]
H A Drtw8723d_table.c10 0x020, 0x00000013,
11 0x02F, 0x00000010,
12 0x077, 0x00000007,
13 0x421, 0x0000000F,
14 0x428, 0x0000000A,
15 0x429, 0x00000010,
16 0x430, 0x00000000,
17 0x431, 0x00000000,
18 0x432, 0x00000000,
19 0x433, 0x00000001,
[all …]
H A Drtw8822b.c54 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8822b_read_efuse()
55 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8822b_read_efuse()
57 efuse->country_code[0] = map->country_code[0]; in rtw8822b_read_efuse()
60 efuse->regd = map->rf_board_option & 0x7; in rtw8822b_read_efuse()
64 for (i = 0; i < 4; i++) in rtw8822b_read_efuse()
82 return 0; in rtw8822b_read_efuse()
88 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
89 rtw_write32_mask(rtwdev, 0x4 in rtw8822b_phy_rfe_init()
[all...]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h7 #define ARAM_CSR_BAR_OFFSET 0x100000
8 #define ADF_C4XXX_REG_SA_CTRL_LOCK (ARAM_CSR_BAR_OFFSET + 0x00)
9 #define ADF_C4XXX_REG_SA_SCRATCH_0 (ARAM_CSR_BAR_OFFSET + 0x04)
10 #define ADF_C4XXX_REG_SA_SCRATCH_2 (ARAM_CSR_BAR_OFFSET + 0x0C)
11 #define ADF_C4XXX_REG_SA_ENTRY_CTRL (ARAM_CSR_BAR_OFFSET + 0x18)
12 #define ADF_C4XXX_REG_SA_DB_CTRL (ARAM_CSR_BAR_OFFSET + 0x1C)
13 #define ADF_C4XXX_REG_SA_REMAP (ARAM_CSR_BAR_OFFSET + 0x20)
14 #define ADF_C4XXX_REG_SA_INLINE_CAPABILITY (ARAM_CSR_BAR_OFFSET + 0x24)
15 #define ADF_C4XXX_REG_SA_INLINE_ENABLE (ARAM_CSR_BAR_OFFSET + 0x28)
16 #define ADF_C4XXX_REG_SA_LINK_UP (ARAM_CSR_BAR_OFFSET + 0x2C)
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-prph.h15 #define PRPH_BASE (0x00000)
16 #define PRPH_END (0xFFFFF)
19 #define APMG_BASE (PRPH_BASE + 0x3000)
20 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
21 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
22 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
23 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
24 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
25 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
26 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001
[all...]
/freebsd/sys/dev/sound/pci/hda/
H A Dhda_reg.h37 #define HDA_CMD_VERB_MASK 0x000fffff
38 #define HDA_CMD_VERB_SHIFT 0
39 #define HDA_CMD_NID_MASK 0x0ff00000
41 #define HDA_CMD_CAD_MASK 0xf0000000
62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00
69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01
70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701
74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0))
80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02
90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03
[all …]
/freebsd/usr.sbin/bhyve/
H A Dhda_reg.h37 #define HDA_CMD_VERB_MASK 0x000fffff
38 #define HDA_CMD_VERB_SHIFT 0
39 #define HDA_CMD_NID_MASK 0x0ff00000
41 #define HDA_CMD_CAD_MASK 0xf0000000
62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00
69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01
70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701
74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0))
80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02
90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/sys/contrib/ena-com/
H A Dena_com.c47 #define ENA_HISTOGRAM_ACTIVE_MASK_OFFSET 0xF08
48 #define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF)
53 #define ENA_CTRL_MAJOR 0
54 #define ENA_CTRL_MINOR 0
67 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
82 #define ENA_PHC_MAX_ERROR_BOUND 0xFFFFFFFF
83 #define ENA_PHC_REQ_ID_OFFSET 0xDEAD
118 if (unlikely((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr)) { in ena_com_mem_addr_set()
126 return 0; in ena_com_mem_addr_set()
143 sq->head = 0; in ena_com_admin_init_sq()
[all …]
/freebsd/sys/dev/cxgbe/common/
H A Dt4_regs.h36 #define MYPF_BASE 0x1b000
39 #define PF0_BASE 0x1e000
42 #define PF1_BASE 0x1e400
45 #define PF2_BASE 0x1e800
48 #define PF3_BASE 0x1ec00
51 #define PF4_BASE 0x1f000
54 #define PF5_BASE 0x1f400
57 #define PF6_BASE 0x1f800
60 #define PF7_BASE 0x1fc00
63 #define PF_STRIDE 0x400
[all …]